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Commit 2c813980 authored by Will Deacon's avatar Will Deacon
Browse files

ARM: tlb: don't perform inner-shareable invalidation for local BP ops 



Now that the ASID allocator doesn't require inner-shareable maintenance,
we can convert the local_bp_flush_all function to perform only
non-shareable flushing, in a similar manner to the TLB invalidation
routines.

Reviewed-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 587b9b64

arch/arm/include/asm/tlbflush.h

+20 −2
Original line number Diff line number Diff line
@@ -531,17 +531,35 @@ static inline void __flush_tlb_kernel_page(unsigned long kaddr) 
 * Branch predictor maintenance is paired with full TLB invalidation, so

 * there is no need for any barriers here.

 */

static inline void __local_flush_bp_all(void)

{

	const int zero = 0;

	const unsigned int __tlb_flag = __cpu_tlb_flags;



	if (tlb_flag(TLB_V6_BP))

		asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero));

}



static inline void local_flush_bp_all(void)

{

	const int zero = 0;

	const unsigned int __tlb_flag = __cpu_tlb_flags;



	__local_flush_bp_all();

	if (tlb_flag(TLB_V7_UIS_BP))

		asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero));

	else if (tlb_flag(TLB_V6_BP))

		asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero));

}



static inline void __flush_bp_all(void)

{

	const int zero = 0;

	const unsigned int __tlb_flag = __cpu_tlb_flags;



	__local_flush_bp_all();

	if (tlb_flag(TLB_V7_UIS_BP))

		asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero));

}



#include <asm/cputype.h>

#ifdef CONFIG_ARM_ERRATA_798181

static inline int erratum_a15_798181(void)

arch/arm/kernel/smp_tlb.c

+1 −1
Original line number Diff line number Diff line
@@ -173,5 +173,5 @@ void flush_bp_all(void) 
	if (tlb_ops_need_broadcast())

		on_each_cpu(ipi_flush_bp_all, NULL, 1);

	else

		local_flush_bp_all();

		__flush_bp_all();

}