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Commit 38489533 authored by Russell King's avatar Russell King
Browse files

ARM: GIC: Remove MMIO address from gic_cpu_init, rename to gic_secondary_init 



We don't need to re-pass the base address for the CPU interfaces to the
GIC for secondary CPUs, as it will never be different from the boot CPU
- and even if it was, we'd overwrite the boot CPU's base address.

Get rid of this argument, and rename to gic_secondary_init().

Reviewed-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Tested-by: default avatarAbhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent b580b899

arch/arm/common/gic.c

+6 −1
Original line number Diff line number Diff line
@@ -284,7 +284,7 @@ static void __init gic_dist_init(unsigned int gic_nr, void __iomem *base, 
	writel(1, base + GIC_DIST_CTRL);

}



void __cpuinit gic_cpu_init(unsigned int gic_nr, void __iomem *base)

static void __cpuinit gic_cpu_init(unsigned int gic_nr, void __iomem *base)

{

	void __iomem *dist_base;

	int i;
@@ -321,6 +321,11 @@ void __init gic_init(unsigned int gic_nr, unsigned int irq_start, 
	gic_cpu_init(gic_nr, cpu_base);

}



void __cpuinit gic_secondary_init(unsigned int gic_nr)

{

	gic_cpu_init(gic_nr, gic_data[gic_nr].cpu_base);

}



#ifdef CONFIG_SMP

void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)

{

arch/arm/include/asm/hardware/gic.h

+1 −1
Original line number Diff line number Diff line
@@ -33,8 +33,8 @@ 
#define GIC_DIST_SOFTINT		0xf00



#ifndef __ASSEMBLY__

void gic_cpu_init(unsigned int gic_nr, void __iomem *base);

void gic_init(unsigned int, unsigned int, void __iomem *, void __iomem *);

void gic_secondary_init(unsigned int);

void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);

void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);

#endif

arch/arm/mach-omap2/omap-smp.c

+1 −1
Original line number Diff line number Diff line
@@ -50,7 +50,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu) 
	 * core (e.g. timer irq), then they will not have been enabled

	 * for us: do so

	 */

	gic_cpu_init(0, gic_cpu_base_addr);

	gic_secondary_init(0);



	/*

	 * Synchronise with the boot thread.

arch/arm/mach-realview/platsmp.c

+1 −1
Original line number Diff line number Diff line
@@ -69,7 +69,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu) 
	 * core (e.g. timer irq), then they will not have been enabled

	 * for us: do so

	 */

	gic_cpu_init(0, gic_cpu_base_addr);

	gic_secondary_init(0);



	/*

	 * let the primary processor know we're out of the

arch/arm/mach-s5pv310/platsmp.c

+1 −1
Original line number Diff line number Diff line
@@ -54,7 +54,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu) 
	 * core (e.g. timer irq), then they will not have been enabled

	 * for us: do so

	 */

	gic_cpu_init(0, gic_cpu_base_addr);

	gic_secondary_init(0);



	/*

	 * let the primary processor know we're out of the