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Commit 32546f38 authored by David Daney's avatar David Daney Committed by Ralf Baechle
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MIPS: Add TLBR and ROTR to uasm. 



The soon to follow Read Inhibit/eXecute Inhibit patch needs TLBR and
ROTR support in uasm.  We also add a UASM_i_ROTR macro.

Signed-off-by: default avatarDavid Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/953/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 9fe2e9d6

arch/mips/include/asm/uasm.h

+4 −0
Original line number Diff line number Diff line
@@ -92,9 +92,11 @@ Ip_u2s3u1(_sd); 
Ip_u2u1u3(_sll);

Ip_u2u1u3(_sra);

Ip_u2u1u3(_srl);

Ip_u2u1u3(_rotr);

Ip_u3u1u2(_subu);

Ip_u2s3u1(_sw);

Ip_0(_tlbp);

Ip_0(_tlbr);

Ip_0(_tlbwi);

Ip_0(_tlbwr);

Ip_u3u1u2(_xor);
@@ -129,6 +131,7 @@ static inline void __cpuinit uasm_l##lb(struct uasm_label **lab, u32 *addr) \ 
# define UASM_i_SLL(buf, rs, rt, sh) uasm_i_dsll(buf, rs, rt, sh)

# define UASM_i_SRA(buf, rs, rt, sh) uasm_i_dsra(buf, rs, rt, sh)

# define UASM_i_SRL(buf, rs, rt, sh) uasm_i_dsrl(buf, rs, rt, sh)

# define UASM_i_ROTR(buf, rs, rt, sh) uasm_i_drotr(buf, rs, rt, sh)

# define UASM_i_MFC0(buf, rt, rd...) uasm_i_dmfc0(buf, rt, rd)

# define UASM_i_MTC0(buf, rt, rd...) uasm_i_dmtc0(buf, rt, rd)

# define UASM_i_ADDIU(buf, rs, rt, val) uasm_i_daddiu(buf, rs, rt, val)
@@ -142,6 +145,7 @@ static inline void __cpuinit uasm_l##lb(struct uasm_label **lab, u32 *addr) \ 
# define UASM_i_SLL(buf, rs, rt, sh) uasm_i_sll(buf, rs, rt, sh)

# define UASM_i_SRA(buf, rs, rt, sh) uasm_i_sra(buf, rs, rt, sh)

# define UASM_i_SRL(buf, rs, rt, sh) uasm_i_srl(buf, rs, rt, sh)

# define UASM_i_ROTR(buf, rs, rt, sh) uasm_i_rotr(buf, rs, rt, sh)

# define UASM_i_MFC0(buf, rt, rd...) uasm_i_mfc0(buf, rt, rd)

# define UASM_i_MTC0(buf, rt, rd...) uasm_i_mtc0(buf, rt, rd)

# define UASM_i_ADDIU(buf, rs, rt, val) uasm_i_addiu(buf, rs, rt, val)

arch/mips/mm/uasm.c

+7 −2
Original line number Diff line number Diff line
@@ -62,8 +62,9 @@ enum opcode { 
	insn_dsrl32, insn_drotr, insn_dsubu, insn_eret, insn_j, insn_jal,

	insn_jr, insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0,

	insn_mtc0, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd,

	insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw,

	insn_tlbp, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori, insn_dins

	insn_sd, insn_sll, insn_sra, insn_srl, insn_rotr, insn_subu, insn_sw,

	insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori,

	insn_dins

};



struct insn {
@@ -125,9 +126,11 @@ static struct insn insn_table[] __cpuinitdata = { 
	{ insn_sll,  M(spec_op, 0, 0, 0, 0, sll_op),  RT | RD | RE },

	{ insn_sra,  M(spec_op, 0, 0, 0, 0, sra_op),  RT | RD | RE },

	{ insn_srl,  M(spec_op, 0, 0, 0, 0, srl_op),  RT | RD | RE },

	{ insn_rotr,  M(spec_op, 1, 0, 0, 0, srl_op),  RT | RD | RE },

	{ insn_subu,  M(spec_op, 0, 0, 0, 0, subu_op),  RS | RT | RD },

	{ insn_sw,  M(sw_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },

	{ insn_tlbp,  M(cop0_op, cop_op, 0, 0, 0, tlbp_op),  0 },

	{ insn_tlbr,  M(cop0_op, cop_op, 0, 0, 0, tlbr_op),  0 },

	{ insn_tlbwi,  M(cop0_op, cop_op, 0, 0, 0, tlbwi_op),  0 },

	{ insn_tlbwr,  M(cop0_op, cop_op, 0, 0, 0, tlbwr_op),  0 },

	{ insn_xor,  M(spec_op, 0, 0, 0, 0, xor_op),  RS | RT | RD },
@@ -378,9 +381,11 @@ I_u2s3u1(_sd) 
I_u2u1u3(_sll)

I_u2u1u3(_sra)

I_u2u1u3(_srl)

I_u2u1u3(_rotr)

I_u3u1u2(_subu)

I_u2s3u1(_sw)

I_0(_tlbp)

I_0(_tlbr)

I_0(_tlbwi)

I_0(_tlbwr)

I_u3u1u2(_xor)