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Commit 2e1aa2a2 authored by Abhijit Kulkarni's avatar Abhijit Kulkarni Committed by Gerrit - the friendly Code Review server
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drm/msm: disp rsc sequence update 



This change updates the mode2 entry and exit sequence for sdm8150.
This is based on recommendatation in hardware programming guide
recommendation.

Change-Id: I131678ff0c1293623e1e2e6c50acf0a454261aef
Signed-off-by: default avatarAbhijit Kulkarni <kabhijit@codeaurora.org>
parent 74219b39

drivers/gpu/drm/msm/sde_power_handle.c

+23 −29
Original line number Diff line number Diff line 
/* Copyright (c) 2014-2017, The Linux Foundation. All rights reserved.

/* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -56,12 +56,9 @@ static void sde_power_event_trigger_locked(struct sde_power_handle *phandle, 
	}

}



static int sde_power_rsc_update(struct sde_power_handle *phandle, bool enable)

static inline void sde_power_rsc_client_init(struct sde_power_handle *phandle)

{

	u32 rsc_state;

	int ret = 0;



	/* creates the rsc client on the first enable */

	/* creates the rsc client */

	if (!phandle->rsc_client_init) {

		phandle->rsc_client = sde_rsc_client_create(SDE_RSC_INDEX,

				"sde_power_handle", false);
@@ -72,6 +69,12 @@ static int sde_power_rsc_update(struct sde_power_handle *phandle, bool enable) 
		}

		phandle->rsc_client_init = true;

	}

}



static int sde_power_rsc_update(struct sde_power_handle *phandle, bool enable)

{

	u32 rsc_state;

	int ret = 0;



	rsc_state = enable ? SDE_RSC_CLK_STATE : SDE_RSC_IDLE_STATE;
@@ -890,6 +893,9 @@ int sde_power_resource_enable(struct sde_power_handle *phandle, 
	if (!changed)

		goto end;



	/* RSC client init */

	sde_power_rsc_client_init(phandle);



	if (enable) {

		sde_power_event_trigger_locked(phandle,

				SDE_POWER_EVENT_PRE_ENABLE);
@@ -903,22 +909,12 @@ int sde_power_resource_enable(struct sde_power_handle *phandle, 
				goto data_bus_hdl_err;

			}

		}

		/*

		 * - When the target is RSCC enabled, regulator should

		 *   be enabled by the s/w only for the first time during

		 *   bootup. After that, RSCC hardware takes care of enabling/

		 *   disabling it.

		 * - When the target is not RSCC enabled, regulator should

		 *   be totally handled by the software.

		 */

		if (!phandle->rsc_client) {

		rc = msm_dss_enable_vreg(mp->vreg_config, mp->num_vreg,

				enable);

		if (rc) {

			pr_err("failed to enable vregs rc=%d\n", rc);

			goto vreg_err;

		}

		}



		rc = sde_power_reg_bus_update(phandle->reg_bus_hdl,

							max_usecase_ndx);
@@ -927,13 +923,13 @@ int sde_power_resource_enable(struct sde_power_handle *phandle, 
			goto reg_bus_hdl_err;

		}



		SDE_EVT32_VERBOSE(enable, SDE_EVTLOG_FUNC_CASE1);

		rc = sde_power_rsc_update(phandle, true);

		if (rc) {

			pr_err("failed to update rsc\n");

			goto rsc_err;

		}



		SDE_EVT32_VERBOSE(enable, SDE_EVTLOG_FUNC_CASE1);

		rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, enable);

		if (rc) {

			pr_err("clock enable failed rc:%d\n", rc);
@@ -948,16 +944,15 @@ int sde_power_resource_enable(struct sde_power_handle *phandle, 
				SDE_POWER_EVENT_PRE_DISABLE);



		SDE_EVT32_VERBOSE(enable, SDE_EVTLOG_FUNC_CASE2);

		msm_dss_enable_clk(mp->clk_config, mp->num_clk, enable);



		sde_power_rsc_update(phandle, false);



		msm_dss_enable_clk(mp->clk_config, mp->num_clk, enable);



		sde_power_reg_bus_update(phandle->reg_bus_hdl,

							max_usecase_ndx);



		if (!phandle->rsc_client)

			msm_dss_enable_vreg(mp->vreg_config, mp->num_vreg,

									enable);

		msm_dss_enable_vreg(mp->vreg_config, mp->num_vreg, enable);



		for (i = 0 ; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)

			sde_power_data_bus_update(&phandle->data_bus_handle[i],

					enable);
@@ -977,7 +972,6 @@ int sde_power_resource_enable(struct sde_power_handle *phandle, 
rsc_err:

	sde_power_reg_bus_update(phandle->reg_bus_hdl, prev_usecase_ndx);

reg_bus_hdl_err:

	if (!phandle->rsc_client)

	msm_dss_enable_vreg(mp->vreg_config, mp->num_vreg, 0);

vreg_err:

	for (i = 0 ; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)

drivers/gpu/drm/msm/sde_rsc_hw.c

+23 −19
Original line number Diff line number Diff line
@@ -191,39 +191,40 @@ static int rsc_hw_seq_memory_init_v2(struct sde_rsc_priv *rsc) 
						0x38bb9ebe, rsc->debug_mode);

	dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_MEM_0_DRV0 + 0x10,

						0xbeff39e0, rsc->debug_mode);



	/* Mode - 2 sequence */

	dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_MEM_0_DRV0 + 0x14,

						0x20209b9e, rsc->debug_mode);



	/* Mode - 2 sequence */

	dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_MEM_0_DRV0 + 0x18,

						0xfab9baa0, rsc->debug_mode);

						0xb9bae5a0, rsc->debug_mode);

	dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_MEM_0_DRV0 + 0x1c,

						0xfebdbbf9, rsc->debug_mode);

						0xbdbbf9fa, rsc->debug_mode);

	dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_MEM_0_DRV0 + 0x20,

						0xa138999a, rsc->debug_mode);

						0x38999afe, rsc->debug_mode);

	dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_MEM_0_DRV0 + 0x24,

						0xa2e081e1, rsc->debug_mode);

						0xac81e1a1, rsc->debug_mode);

	dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_MEM_0_DRV0 + 0x28,

						0x9d3982e2, rsc->debug_mode);



	/* tcs sleep & wake sequence */

						0x82e2a2e0, rsc->debug_mode);

	dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_MEM_0_DRV0 + 0x2c,

						0x20209bfd, rsc->debug_mode);

						0x8cfd9d39, rsc->debug_mode);

	dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_MEM_0_DRV0 + 0x30,

						0x01a6fcbc, rsc->debug_mode);

						0xbc20209b, rsc->debug_mode);



	/* tcs sleep & wake sequence */

	dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_MEM_0_DRV0 + 0x34,

						0x20209ce6, rsc->debug_mode);

						0xe601a6fc, rsc->debug_mode);

	dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_MEM_0_DRV0 + 0x38,

						0x01a7fcbc, rsc->debug_mode);

						0xbc20209c, rsc->debug_mode);

	dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_MEM_0_DRV0 + 0x3c,

						0x00209ce7, rsc->debug_mode);



						0xe701a7fc, rsc->debug_mode);

	dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_MEM_0_DRV0 + 0x40,

						0x0000209c, rsc->debug_mode);



	/* branch address */

	dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_CFG_BR_ADDR_0_DRV0,

						0x30, rsc->debug_mode);

						0x33, rsc->debug_mode);

	dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_CFG_BR_ADDR_1_DRV0,

						0x38, rsc->debug_mode);

						0x3b, rsc->debug_mode);



	/* start address */

	dss_reg_w(&rsc->drv_io, SDE_RSC_SOLVER_OVERRIDE_CTRL_DRV0,
@@ -550,8 +551,11 @@ static int sde_rsc_mode2_entry(struct sde_rsc_priv *rsc) 
	}



	if (rc) {

		pr_err("mdss gdsc power down failed rc:%d\n", rc);

		SDE_EVT32(rc, SDE_EVTLOG_ERROR);

		reg = dss_reg_r(&rsc->drv_io,

				SDE_RSCC_SEQ_PROGRAM_COUNTER, rsc->debug_mode);

		pr_err("mdss gdsc power down failed, instruction:0x%x, rc:%d\n",

				reg, rc);

		SDE_EVT32(rc, reg, SDE_EVTLOG_ERROR);

		goto end;

	}