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Commit 2806683c authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'imx-soc' of git://git.pengutronix.de/git/imx/linux-2.6 into next/soc 

From Sascha Hauer:
ARM i.MX SoC updates for next

Mostly clock related updates, most notably the conversion of
i.MX31 to a DT based lookup.

* tag 'imx-soc' of git://git.pengutronix.de/git/imx/linux-2.6

:
  ARM: clk-imx35: Fix build warnings with W=1
  ARM: imx27: add a clock gate to activate SPLL clock
  ARM: mx31: Replace clk_register_clkdev with clock DT lookup
  ARM: clk-imx31: Add dummy clock
  ARM: Let CONFIG_MACH_IMX31_DT be built by default

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents af70fdc9 3ea80985

Documentation/devicetree/bindings/clock/imx31-clock.txt

0 → 100644
+91 −0
Original line number Diff line number Diff line 
* Clock bindings for Freescale i.MX31



Required properties:

- compatible: Should be "fsl,imx31-ccm"

- reg: Address and length of the register set

- interrupts: Should contain CCM interrupt

- #clock-cells: Should be <1>



The clock consumer should specify the desired clock by having the clock

ID in its "clocks" phandle cell.  The following is a full list of i.MX31

clocks and IDs.



	Clock		    ID

	-----------------------

	dummy	             0

	ckih                 1

	ckil                 2

	mpll                 3

	spll                 4

	upll                 5

	mcu_main             6

	hsp                  7

	ahb                  8

	nfc                  9

	ipg                  10

	per_div              11

	per                  12

	csi_sel              13

	fir_sel              14

	csi_div              15

	usb_div_pre          16

	usb_div_post         17

	fir_div_pre          18

	fir_div_post         19

	sdhc1_gate           20

	sdhc2_gate           21

	gpt_gate             22

	epit1_gate           23

	epit2_gate           24

	iim_gate             25

	ata_gate             26

	sdma_gate            27

	cspi3_gate           28

	rng_gate             29

	uart1_gate           30

	uart2_gate           31

	ssi1_gate            32

	i2c1_gate            33

	i2c2_gate            34

	i2c3_gate            35

	hantro_gate          36

	mstick1_gate         37

	mstick2_gate         38

	csi_gate             39

	rtc_gate             40

	wdog_gate            41

	pwm_gate             42

	sim_gate             43

	ect_gate             44

	usb_gate             45

	kpp_gate             46

	ipu_gate             47

	uart3_gate           48

	uart4_gate           49

	uart5_gate           50

	owire_gate           51

	ssi2_gate            52

	cspi1_gate           53

	cspi2_gate           54

	gacc_gate            55

	emi_gate             56

	rtic_gate            57

	firi_gate            58



Examples:



clks: ccm@53f80000{

	compatible = "fsl,imx31-ccm";

	reg = <0x53f80000 0x4000>;

	interrupts = <0 31 0x04 0 53 0x04>;

	#clock-cells = <1>;

};



uart1: serial@43f90000 {

	compatible = "fsl,imx31-uart", "fsl,imx21-uart";

	reg = <0x43f90000 0x4000>;

	interrupts = <45>;

	clocks = <&clks 10>, <&clks 30>;

	clock-names = "ipg", "per";

	status = "disabled";

};

arch/arm/boot/dts/imx31.dtsi

+17 −0
Original line number Diff line number Diff line
@@ -45,6 +45,8 @@ 
				compatible = "fsl,imx31-uart", "fsl,imx21-uart";

				reg = <0x43f90000 0x4000>;

				interrupts = <45>;

				clocks = <&clks 10>, <&clks 30>;

				clock-names = "ipg", "per";

				status = "disabled";

			};
@@ -52,12 +54,16 @@ 
				compatible = "fsl,imx31-uart", "fsl,imx21-uart";

				reg = <0x43f94000 0x4000>;

				interrupts = <32>;

				clocks = <&clks 10>, <&clks 31>;

				clock-names = "ipg", "per";

				status = "disabled";

			};



			uart4: serial@43fb0000 {

				compatible = "fsl,imx31-uart", "fsl,imx21-uart";

				reg = <0x43fb0000 0x4000>;

				clocks = <&clks 10>, <&clks 49>;

				clock-names = "ipg", "per";

				interrupts = <46>;

				status = "disabled";

			};
@@ -66,6 +72,8 @@ 
				compatible = "fsl,imx31-uart", "fsl,imx21-uart";

				reg = <0x43fb4000 0x4000>;

				interrupts = <47>;

				clocks = <&clks 10>, <&clks 50>;

				clock-names = "ipg", "per";

				status = "disabled";

			};

		};
@@ -81,8 +89,17 @@ 
				compatible = "fsl,imx31-uart", "fsl,imx21-uart";

				reg = <0x5000c000 0x4000>;

				interrupts = <18>;

				clocks = <&clks 10>, <&clks 48>;

				clock-names = "ipg", "per";

				status = "disabled";

			};



			clks: ccm@53f80000{

				compatible = "fsl,imx31-ccm";

				reg = <0x53f80000 0x4000>;

				interrupts = <0 31 0x04 0 53 0x04>;

				#clock-cells = <1>;

			};

		};

	};

};

arch/arm/configs/imx_v6_v7_defconfig

+1 −0
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@ CONFIG_MODULE_SRCVERSION_ALL=y 
CONFIG_ARCH_MXC=y

CONFIG_ARCH_MULTI_V6=y

CONFIG_ARCH_MULTI_V7=y

CONFIG_MACH_IMX31_DT=y

CONFIG_MACH_MX31LILLY=y

CONFIG_MACH_MX31LITE=y

CONFIG_MACH_PCM037=y

arch/arm/mach-imx/clk-imx27.c

+4 −3
Original line number Diff line number Diff line
@@ -62,7 +62,7 @@ static const char *clko_sel_clks[] = { 
	"32k", "usb_div", "dptc",

};



static const char *ssi_sel_clks[] = { "spll", "mpll", };

static const char *ssi_sel_clks[] = { "spll_gate", "mpll", };



enum mx27_clks {

	dummy, ckih, ckil, mpll, spll, mpll_main2, ahb, ipg, nfc_div, per1_div,
@@ -82,7 +82,7 @@ enum mx27_clks { 
	csi_ahb_gate, brom_ahb_gate, ata_ahb_gate, wdog_ipg_gate, usb_ipg_gate,

	uart6_ipg_gate, uart5_ipg_gate, uart4_ipg_gate, uart3_ipg_gate,

	uart2_ipg_gate, uart1_ipg_gate, ckih_div1p5, fpm, mpll_osc_sel,

	mpll_sel, clk_max

	mpll_sel, spll_gate, clk_max

};



static struct clk *clk[clk_max];
@@ -104,6 +104,7 @@ int __init mx27_clocks_init(unsigned long fref) 
			ARRAY_SIZE(mpll_sel_clks));

	clk[mpll] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);

	clk[spll] = imx_clk_pllv1("spll", "ckih", CCM_SPCTL0);

	clk[spll_gate] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);

	clk[mpll_main2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3);



	if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
@@ -121,7 +122,7 @@ int __init mx27_clocks_init(unsigned long fref) 
	clk[per4_div] = imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6);

	clk[vpu_sel] = imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks));

	clk[vpu_div] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 6);

	clk[usb_div] = imx_clk_divider("usb_div", "spll", CCM_CSCR, 28, 3);

	clk[usb_div] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 28, 3);

	clk[cpu_sel] = imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks));

	clk[clko_sel] = imx_clk_mux("clko_sel", CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks));

	if (mx27_revision() >= IMX_CHIP_REVISION_2_0)

arch/arm/mach-imx/clk-imx31.c

+13 −2
Original line number Diff line number Diff line
@@ -34,8 +34,8 @@ static const char *csi_sel[] = { "upll", "spll", }; 
static const char *fir_sel[] = { "mcu_main", "upll", "spll" };



enum mx31_clks {

	ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg, per_div,

	per, csi, fir, csi_div, usb_div_pre, usb_div_post, fir_div_pre,

	dummy, ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg,

	per_div, per, csi, fir, csi_div, usb_div_pre, usb_div_post, fir_div_pre,

	fir_div_post, sdhc1_gate, sdhc2_gate, gpt_gate, epit1_gate, epit2_gate,

	iim_gate, ata_gate, sdma_gate, cspi3_gate, rng_gate, uart1_gate,

	uart2_gate, ssi1_gate, i2c1_gate, i2c2_gate, i2c3_gate, hantro_gate,
@@ -46,12 +46,15 @@ enum mx31_clks { 
};



static struct clk *clk[clk_max];

static struct clk_onecell_data clk_data;



int __init mx31_clocks_init(unsigned long fref)

{

	void __iomem *base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR);

	int i;

	struct device_node *np;



	clk[dummy] = imx_clk_fixed("dummy", 0);

	clk[ckih] = imx_clk_fixed("ckih", fref);

	clk[ckil] = imx_clk_fixed("ckil", 32768);

	clk[mpll] = imx_clk_pllv1("mpll", "ckih", base + MXC_CCM_MPCTL);
@@ -116,6 +119,14 @@ int __init mx31_clocks_init(unsigned long fref) 
			pr_err("imx31 clk %d: register failed with %ld\n",

				i, PTR_ERR(clk[i]));



	np = of_find_compatible_node(NULL, NULL, "fsl,imx31-ccm");



	if (np) {

		clk_data.clks = clk;

		clk_data.clk_num = ARRAY_SIZE(clk);

		of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);

	}



	clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0");

	clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");

	clk_register_clkdev(clk[cspi1_gate], NULL, "imx31-cspi.0");