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Commit 274c34db authored by Jyri Sarha's avatar Jyri Sarha
Browse files

drm/tilcdc: Load palette at the end of mode_set_nofb() 



Load palette at the end of mode_set_nofb(). Moving the palette loading
to mode_set_nofb() saves us from storing and restoring of framebuffer
addresses in dma registers that were just recently written there.

Signed-off-by: default avatarJyri Sarha <jsarha@ti.com>
Tested-by: default avatarBartosz Golaszewski <bgolaszewski@baylibre.com>
parent e59f5af9

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

+5 −20
Original line number Original line Diff line number Diff line
@@ -121,15 +121,12 @@ static void set_scanout(struct drm_crtc *crtc, struct drm_framebuffer *fb) 
 */

 */

static void tilcdc_crtc_load_palette(struct drm_crtc *crtc)

static void tilcdc_crtc_load_palette(struct drm_crtc *crtc)

{

{

	u32 dma_fb_base, dma_fb_ceiling, raster_ctl;

	struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);

	struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);

	struct drm_device *dev = crtc->dev;

	struct drm_device *dev = crtc->dev;

	struct tilcdc_drm_private *priv = dev->dev_private;

	struct tilcdc_drm_private *priv = dev->dev_private;

	int ret;

	int ret;





	dma_fb_base = tilcdc_read(dev, LCDC_DMA_FB_BASE_ADDR_0_REG);

	reinit_completion(&tilcdc_crtc->palette_loaded);

	dma_fb_ceiling = tilcdc_read(dev, LCDC_DMA_FB_CEILING_ADDR_0_REG);

	raster_ctl = tilcdc_read(dev, LCDC_RASTER_CTRL_REG);





	/* Tell the LCDC where the palette is located. */

	/* Tell the LCDC where the palette is located. */

	tilcdc_write(dev, LCDC_DMA_FB_BASE_ADDR_0_REG,

	tilcdc_write(dev, LCDC_DMA_FB_BASE_ADDR_0_REG,
@@ -164,11 +161,6 @@ static void tilcdc_crtc_load_palette(struct drm_crtc *crtc) 
		tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_PL_INT_ENA);

		tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_PL_INT_ENA);

	else

	else

		tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG, LCDC_V2_PL_INT_ENA);

		tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG, LCDC_V2_PL_INT_ENA);



	/* Restore the registers. */

	tilcdc_write(dev, LCDC_DMA_FB_BASE_ADDR_0_REG, dma_fb_base);

	tilcdc_write(dev, LCDC_DMA_FB_CEILING_ADDR_0_REG, dma_fb_ceiling);

	tilcdc_write(dev, LCDC_RASTER_CTRL_REG, raster_ctl);

}

}





static void tilcdc_crtc_enable_irqs(struct drm_device *dev)

static void tilcdc_crtc_enable_irqs(struct drm_device *dev)
@@ -239,9 +231,6 @@ static void tilcdc_crtc_enable(struct drm_crtc *crtc) 




	reset(crtc);

	reset(crtc);





	if (!completion_done(&tilcdc_crtc->palette_loaded))

		tilcdc_crtc_load_palette(crtc);



	tilcdc_crtc_enable_irqs(dev);

	tilcdc_crtc_enable_irqs(dev);





	tilcdc_clear(dev, LCDC_DMA_CTRL_REG, LCDC_DUAL_FRAME_BUFFER_ENABLE);

	tilcdc_clear(dev, LCDC_DMA_CTRL_REG, LCDC_DUAL_FRAME_BUFFER_ENABLE);
@@ -285,12 +274,6 @@ static void tilcdc_crtc_off(struct drm_crtc *crtc, bool shutdown) 
				__func__);

				__func__);

	}

	}





	/*

	 * LCDC will not retain the palette when reset. Make sure it gets

	 * reloaded on tilcdc_crtc_enable().

	 */

	reinit_completion(&tilcdc_crtc->palette_loaded);



	drm_crtc_vblank_off(crtc);

	drm_crtc_vblank_off(crtc);





	tilcdc_crtc_disable_irqs(dev);

	tilcdc_crtc_disable_irqs(dev);
@@ -678,10 +661,12 @@ static void tilcdc_crtc_mode_set_nofb(struct drm_crtc *crtc) 




	drm_framebuffer_reference(fb);

	drm_framebuffer_reference(fb);





	set_scanout(crtc, fb);



	tilcdc_crtc_set_clk(crtc);

	tilcdc_crtc_set_clk(crtc);





	tilcdc_crtc_load_palette(crtc);



	set_scanout(crtc, fb);



	crtc->hwmode = crtc->state->adjusted_mode;

	crtc->hwmode = crtc->state->adjusted_mode;

}

}