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Commit 1f63e2ff authored by Deepak Katragadda's avatar Deepak Katragadda Committed by Gerrit - the friendly Code Review server
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clk: qcom: gpucc-sdm855: Add GPU clock driver support for SDMSHRIKE 



There are a few changes in the frequency plan for Graphics between
SDM855 and SDMSHRIKE. Pull those change into the graphics clock
driver and enable support for SDMSHRIKE.

Change-Id: I3829114b753861aa134325bbf8cc8e0c95694d07
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent d732694b

Documentation/devicetree/bindings/clock/qcom,gpucc.txt

+3 −2
Original line number Diff line number Diff line
@@ -2,8 +2,9 @@ Qualcomm Technologies, Inc. Graphics Clock & Reset Controller Binding 
--------------------------------------------------------------------



Required properties :

- compatible : shall contain :

		"qcom,gpucc-sdm855"

- compatible : shall contain one of the following:

		"qcom,gpucc-sdm855",

		"qcom,gpucc-sdmshrike".



- reg : shall contain base register offset and size.

- reg-names: names of registers listed in the same order as in the reg property.

drivers/clk/qcom/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -292,7 +292,7 @@ config MSM_CLK_RPMH 


config MSM_GPUCC_SDM855

	tristate "SDM855 Graphics Clock Controller"

	depends on MSM_GCC_SDM855

	depends on COMMON_CLK_QCOM

	help

	  Support for the graphics clock controller on Qualcomm Technologies, Inc.

	  sdm855 devices.

drivers/clk/qcom/gpucc-sdm855.c

+33 −0
Original line number Diff line number Diff line
@@ -115,6 +115,14 @@ static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { 
	{ }

};



static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src_sdmshrike[] = {

	F(19200000, P_BI_TCXO, 1, 0, 0),

	F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),

	F(400000000, P_GPLL0_OUT_MAIN, 1.5, 0, 0),

	F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),

	{ }

};



static struct clk_rcg2 gpu_cc_gmu_clk_src = {

	.cmd_rcgr = 0x1120,

	.mnd_width = 0,
@@ -415,10 +423,33 @@ static const struct qcom_cc_desc gpu_cc_sdm855_desc = { 


static const struct of_device_id gpu_cc_sdm855_match_table[] = {

	{ .compatible = "qcom,gpucc-sdm855" },

	{ .compatible = "qcom,gpucc-sdmshrike" },

	{ }

};

MODULE_DEVICE_TABLE(of, gpu_cc_sdm855_match_table);



static void gpu_cc_sdm855_fixup_sdmshrike(void)

{

	gpu_cc_gmu_clk_src.freq_tbl = ftbl_gpu_cc_gmu_clk_src_sdmshrike;

	gpu_cc_gmu_clk_src.clkr.hw.init->rate_max[VDD_LOW] = 400000000;

	gpu_cc_gmu_clk_src.clkr.hw.init->rate_max[VDD_LOW_L1] = 500000000;

}



static int gpu_cc_sdm855_fixup(struct platform_device *pdev)

{

	const char *compat = NULL;

	int compatlen = 0;



	compat = of_get_property(pdev->dev.of_node, "compatible", &compatlen);

	if (!compat || (compatlen <= 0))

		return -EINVAL;



	if (!strcmp(compat, "qcom,gpucc-sdmshrike"))

		gpu_cc_sdm855_fixup_sdmshrike();



	return 0;

}



static int gpu_cc_sdm855_probe(struct platform_device *pdev)

{

	struct regmap *regmap;
@@ -446,6 +477,8 @@ static int gpu_cc_sdm855_probe(struct platform_device *pdev) 


	clk_trion_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);



	gpu_cc_sdm855_fixup(pdev);



	ret = qcom_cc_really_probe(pdev, &gpu_cc_sdm855_desc, regmap);

	if (ret) {

		dev_err(&pdev->dev, "Failed to register GPU CC clocks\n");