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Commit 1f58af30 authored by Zhao Yan's avatar Zhao Yan Committed by Zhenyu Wang
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drm/i915/gvt: fix an error for one register 



register 0x20e0 should be mode register

v2: rebased to latest code base

Signed-off-by: default avatarZhao Yan <yan.y.zhao@intel.com>
Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
parent 9112caaf

drivers/gpu/drm/i915/gvt/handlers.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -2749,7 +2749,7 @@ static int init_skl_mmio_info(struct intel_gvt *gvt) 
	MMIO_F(0xb020, 0x80, F_CMD_ACCESS, 0, 0, D_SKL, NULL, NULL);

	MMIO_F(0xb020, 0x80, F_CMD_ACCESS, 0, 0, D_SKL, NULL, NULL);





	MMIO_D(0xd08, D_SKL);

	MMIO_D(0xd08, D_SKL);

	MMIO_D(0x20e0, D_SKL);

	MMIO_DFH(0x20e0, D_SKL, F_MODE_MASK, NULL, NULL);

	MMIO_DFH(0x20ec, D_SKL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

	MMIO_DFH(0x20ec, D_SKL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);





	/* TRTT */

	/* TRTT */