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Commit 9112caaf authored by Zhao Yan's avatar Zhao Yan Committed by Zhenyu Wang
Browse files

drm/i915/gvt: add more registers into handlers list 



those registers are render registers with F_CMD_ACCESS flag set

Signed-off-by: default avatarZhao Yan <yan.y.zhao@intel.com>
Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
parent 0aa5277c

drivers/gpu/drm/i915/gvt/handlers.c

+22 −0
Original line number Diff line number Diff line
@@ -2332,6 +2332,17 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) 
	MMIO_DH(0x4270, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);

	MMIO_DFH(0x4094, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);



	MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

	MMIO_RING_GM_RDR(RING_BBADDR, D_ALL, NULL, NULL);

	MMIO_DFH(0x2220, D_ALL, F_CMD_ACCESS, NULL, NULL);

	MMIO_DFH(0x12220, D_ALL, F_CMD_ACCESS, NULL, NULL);

	MMIO_DFH(0x22220, D_ALL, F_CMD_ACCESS, NULL, NULL);

	MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);

	MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);

	MMIO_DFH(0x22178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);

	MMIO_DFH(0x1a178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);

	MMIO_DFH(0x1a17c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);

	MMIO_DFH(0x2217c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);

	return 0;

}
@@ -2550,6 +2561,15 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt) 


	MMIO_DFH(0x2248, D_BDW, F_CMD_ACCESS, NULL, NULL);



	MMIO_DFH(0xe220, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);

	MMIO_DFH(0xe230, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);

	MMIO_DFH(0xe240, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);

	MMIO_DFH(0xe260, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);

	MMIO_DFH(0xe270, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);

	MMIO_DFH(0xe280, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);

	MMIO_DFH(0xe2a0, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);

	MMIO_DFH(0xe2b0, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);

	MMIO_DFH(0xe2c0, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);

	return 0;

}
@@ -2776,6 +2796,8 @@ static int init_skl_mmio_info(struct intel_gvt *gvt) 


	MMIO_D(0x44500, D_SKL);

	MMIO_DFH(GEN9_CSFE_CHICKEN1_RCS, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);

	MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL, F_MODE_MASK | F_CMD_ACCESS,

		NULL, NULL);

	return 0;

}