Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 187e3593 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon: rework GPU reset on cayman/TN 



Update the code to better match the recommended
programming sequence for soft reset.

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b7630473

drivers/gpu/drm/radeon/evergreen.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -2327,7 +2327,7 @@ bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *rin 
	return radeon_ring_test_lockup(rdev, ring);

	return radeon_ring_test_lockup(rdev, ring);

}

}





static void evergreen_print_gpu_status_regs(struct radeon_device *rdev)

void evergreen_print_gpu_status_regs(struct radeon_device *rdev)

{

{

	dev_info(rdev->dev, "  GRBM_STATUS               = 0x%08X\n",

	dev_info(rdev->dev, "  GRBM_STATUS               = 0x%08X\n",

		RREG32(GRBM_STATUS));

		RREG32(GRBM_STATUS));

drivers/gpu/drm/radeon/ni.c

+91 −107
Original line number Original line Diff line number Diff line
@@ -34,6 +34,7 @@ 
#include "ni_reg.h"

#include "ni_reg.h"

#include "cayman_blit_shaders.h"

#include "cayman_blit_shaders.h"





extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);

extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);

extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);

extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);

extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);

extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev);

extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
@@ -1310,84 +1311,45 @@ void cayman_dma_fini(struct radeon_device *rdev) 
	radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]);

	radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]);

}

}





static void cayman_gpu_soft_reset_gfx(struct radeon_device *rdev)

static int cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)

{

{

	u32 grbm_reset = 0;

	struct evergreen_mc_save save;

	u32 grbm_soft_reset = 0, srbm_soft_reset = 0;

	u32 tmp;

	int ret = 0;





	if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))

	if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))

		return;

		reset_mask &= ~(RADEON_RESET_GFX | RADEON_RESET_COMPUTE | RADEON_RESET_CP);





	dev_info(rdev->dev, "  GRBM_STATUS               = 0x%08X\n",

	if (RREG32(DMA_STATUS_REG) & DMA_IDLE)

		RREG32(GRBM_STATUS));

		reset_mask &= ~RADEON_RESET_DMA;

	dev_info(rdev->dev, "  GRBM_STATUS_SE0           = 0x%08X\n",

		RREG32(GRBM_STATUS_SE0));

	dev_info(rdev->dev, "  GRBM_STATUS_SE1           = 0x%08X\n",

		RREG32(GRBM_STATUS_SE1));

	dev_info(rdev->dev, "  SRBM_STATUS               = 0x%08X\n",

		RREG32(SRBM_STATUS));

	dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",

		RREG32(CP_STALLED_STAT1));

	dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",

		RREG32(CP_STALLED_STAT2));

	dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",

		RREG32(CP_BUSY_STAT));

	dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",

		RREG32(CP_STAT));





	/* Disable CP parsing/prefetching */

	if (reset_mask == 0)

	WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);

		return 0;





	/* reset all the gfx blocks */

	dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);

	grbm_reset = (SOFT_RESET_CP |

		      SOFT_RESET_CB |

		      SOFT_RESET_DB |

		      SOFT_RESET_GDS |

		      SOFT_RESET_PA |

		      SOFT_RESET_SC |

		      SOFT_RESET_SPI |

		      SOFT_RESET_SH |

		      SOFT_RESET_SX |

		      SOFT_RESET_TC |

		      SOFT_RESET_TA |

		      SOFT_RESET_VGT |

		      SOFT_RESET_IA);





	dev_info(rdev->dev, "  GRBM_SOFT_RESET=0x%08X\n", grbm_reset);

	evergreen_print_gpu_status_regs(rdev);

	WREG32(GRBM_SOFT_RESET, grbm_reset);

	dev_info(rdev->dev, "  VM_CONTEXT0_PROTECTION_FAULT_ADDR   0x%08X\n",

	(void)RREG32(GRBM_SOFT_RESET);

		 RREG32(0x14F8));

	udelay(50);

	dev_info(rdev->dev, "  VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",

	WREG32(GRBM_SOFT_RESET, 0);

		 RREG32(0x14D8));

	(void)RREG32(GRBM_SOFT_RESET);

	dev_info(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",



		 RREG32(0x14FC));

	dev_info(rdev->dev, "  GRBM_STATUS               = 0x%08X\n",

	dev_info(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",

		RREG32(GRBM_STATUS));

		 RREG32(0x14DC));

	dev_info(rdev->dev, "  GRBM_STATUS_SE0           = 0x%08X\n",

		RREG32(GRBM_STATUS_SE0));

	dev_info(rdev->dev, "  GRBM_STATUS_SE1           = 0x%08X\n",

		RREG32(GRBM_STATUS_SE1));

	dev_info(rdev->dev, "  SRBM_STATUS               = 0x%08X\n",

		RREG32(SRBM_STATUS));

	dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",

		RREG32(CP_STALLED_STAT1));

	dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",

		RREG32(CP_STALLED_STAT2));

	dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",

		RREG32(CP_BUSY_STAT));

	dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",

		RREG32(CP_STAT));



}



static void cayman_gpu_soft_reset_dma(struct radeon_device *rdev)

{

	u32 tmp;





	if (RREG32(DMA_STATUS_REG) & DMA_IDLE)

	r600_set_bios_scratch_engine_hung(rdev, true);

		return;





	dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",

	evergreen_mc_stop(rdev, &save);

		RREG32(DMA_STATUS_REG));

	if (evergreen_mc_wait_for_idle(rdev)) {

		dev_warn(rdev->dev, "Wait for MC idle timedout !\n");

	}



	/* Disable CP parsing/prefetching */

	WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);





	if (reset_mask & RADEON_RESET_DMA) {

		/* dma0 */

		/* dma0 */

		tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);

		tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);

		tmp &= ~DMA_RB_ENABLE;

		tmp &= ~DMA_RB_ENABLE;
@@ -1397,62 +1359,83 @@ static void cayman_gpu_soft_reset_dma(struct radeon_device *rdev) 
		tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);

		tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);

		tmp &= ~DMA_RB_ENABLE;

		tmp &= ~DMA_RB_ENABLE;

		WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);

		WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);

	}





	/* Reset dma */

	if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {

	WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1);

		grbm_soft_reset = SOFT_RESET_CB |

	RREG32(SRBM_SOFT_RESET);

			SOFT_RESET_DB |

	udelay(50);

			SOFT_RESET_GDS |

	WREG32(SRBM_SOFT_RESET, 0);

			SOFT_RESET_PA |

			SOFT_RESET_SC |

			SOFT_RESET_SPI |

			SOFT_RESET_SH |

			SOFT_RESET_SX |

			SOFT_RESET_TC |

			SOFT_RESET_TA |

			SOFT_RESET_VGT |

			SOFT_RESET_IA;

	}





	dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",

	if (reset_mask & RADEON_RESET_CP) {

		RREG32(DMA_STATUS_REG));

		grbm_soft_reset |= SOFT_RESET_CP | SOFT_RESET_VGT;





		srbm_soft_reset |= SOFT_RESET_GRBM;

	}

	}





static int cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)

	if (reset_mask & RADEON_RESET_DMA)

{

		srbm_soft_reset |= SOFT_RESET_DMA | SOFT_RESET_DMA1;

	struct evergreen_mc_save save;



	if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))

		reset_mask &= ~(RADEON_RESET_GFX | RADEON_RESET_COMPUTE);





	if (RREG32(DMA_STATUS_REG) & DMA_IDLE)

	if (grbm_soft_reset) {

		reset_mask &= ~RADEON_RESET_DMA;

		tmp = RREG32(GRBM_SOFT_RESET);

		tmp |= grbm_soft_reset;

		dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);

		WREG32(GRBM_SOFT_RESET, tmp);

		tmp = RREG32(GRBM_SOFT_RESET);





	if (reset_mask == 0)

		udelay(50);

		return 0;





	r600_set_bios_scratch_engine_hung(rdev, true);

		tmp &= ~grbm_soft_reset;

		WREG32(GRBM_SOFT_RESET, tmp);

		tmp = RREG32(GRBM_SOFT_RESET);

	}





	dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);

	if (srbm_soft_reset) {

		tmp = RREG32(SRBM_SOFT_RESET);

		tmp |= srbm_soft_reset;

		dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);

		WREG32(SRBM_SOFT_RESET, tmp);

		tmp = RREG32(SRBM_SOFT_RESET);





	dev_info(rdev->dev, "  VM_CONTEXT0_PROTECTION_FAULT_ADDR   0x%08X\n",

		udelay(50);

		 RREG32(0x14F8));

	dev_info(rdev->dev, "  VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",

		 RREG32(0x14D8));

	dev_info(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",

		 RREG32(0x14FC));

	dev_info(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",

		 RREG32(0x14DC));





	evergreen_mc_stop(rdev, &save);

		tmp &= ~srbm_soft_reset;

	if (evergreen_mc_wait_for_idle(rdev)) {

		WREG32(SRBM_SOFT_RESET, tmp);

		dev_warn(rdev->dev, "Wait for MC idle timedout !\n");

		tmp = RREG32(SRBM_SOFT_RESET);

	}

	}





	if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE))

		cayman_gpu_soft_reset_gfx(rdev);



	if (reset_mask & RADEON_RESET_DMA)

		cayman_gpu_soft_reset_dma(rdev);



	/* Wait a little for things to settle down */

	/* Wait a little for things to settle down */

	udelay(50);

	udelay(50);





	evergreen_mc_resume(rdev, &save);

	evergreen_mc_resume(rdev, &save);

	udelay(50);





#if 0

	if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE | RADEON_RESET_CP)) {

		if (RREG32(GRBM_STATUS) & GUI_ACTIVE)

			ret = -EAGAIN;

	}



	if (reset_mask & RADEON_RESET_DMA) {

		if (!(RREG32(DMA_STATUS_REG) & DMA_IDLE))

			ret = -EAGAIN;

	}

#endif



	if (!ret)

		r600_set_bios_scratch_engine_hung(rdev, false);

		r600_set_bios_scratch_engine_hung(rdev, false);





	evergreen_print_gpu_status_regs(rdev);



	return 0;

	return 0;

}

}
@@ -1460,7 +1443,8 @@ int cayman_asic_reset(struct radeon_device *rdev) 
{

{

	return cayman_gpu_soft_reset(rdev, (RADEON_RESET_GFX |

	return cayman_gpu_soft_reset(rdev, (RADEON_RESET_GFX |

					    RADEON_RESET_COMPUTE |

					    RADEON_RESET_COMPUTE |

					    RADEON_RESET_DMA));

					    RADEON_RESET_DMA |

					    RADEON_RESET_CP));

}

}





/**

/**