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Commit 124904ee authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add tupwr-disable for SM8150, SM6150 and SDMMAGPIE"

parents e5728a8c 32728e2a

arch/arm64/boot/dts/qcom/sdmmagpie-coresight.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -1186,6 +1186,7 @@ 
		reg = <0x7040000 0x1000>;

		cpu = <&CPU0>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm0";



		clocks = <&clock_aop QDSS_CLK>;
@@ -1205,6 +1206,7 @@ 
		reg = <0x7140000 0x1000>;

		cpu = <&CPU1>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm1";



		clocks = <&clock_aop QDSS_CLK>;
@@ -1224,6 +1226,7 @@ 
		reg = <0x7240000 0x1000>;

		cpu = <&CPU2>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm2";



		clocks = <&clock_aop QDSS_CLK>;
@@ -1243,6 +1246,7 @@ 
		reg = <0x7340000 0x1000>;

		cpu = <&CPU3>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm3";



		clocks = <&clock_aop QDSS_CLK>;
@@ -1262,6 +1266,7 @@ 
		reg = <0x7440000 0x1000>;

		cpu = <&CPU4>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm4";



		clocks = <&clock_aop QDSS_CLK>;
@@ -1281,6 +1286,7 @@ 
		reg = <0x7540000 0x1000>;

		cpu = <&CPU5>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm5";



		clocks = <&clock_aop QDSS_CLK>;
@@ -1300,6 +1306,7 @@ 
		reg = <0x7640000 0x1000>;

		cpu = <&CPU6>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm6";



		clocks = <&clock_aop QDSS_CLK>;
@@ -1319,6 +1326,7 @@ 
		reg = <0x7740000 0x1000>;

		cpu = <&CPU7>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm7";



		clocks = <&clock_aop QDSS_CLK>;

arch/arm64/boot/dts/qcom/sm6150-coresight.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -1896,6 +1896,7 @@ 
		reg = <0x7040000 0x1000>;

		cpu = <&CPU0>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm0";



		clocks = <&clock_aop QDSS_CLK>;
@@ -1915,6 +1916,7 @@ 
		reg = <0x7140000 0x1000>;

		cpu = <&CPU1>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm1";



		clocks = <&clock_aop QDSS_CLK>;
@@ -1934,6 +1936,7 @@ 
		reg = <0x7240000 0x1000>;

		cpu = <&CPU2>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm2";



		clocks = <&clock_aop QDSS_CLK>;
@@ -1953,6 +1956,7 @@ 
		reg = <0x7340000 0x1000>;

		cpu = <&CPU3>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm3";



		clocks = <&clock_aop QDSS_CLK>;
@@ -1972,6 +1976,7 @@ 
		reg = <0x7440000 0x1000>;

		cpu = <&CPU4>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm4";



		clocks = <&clock_aop QDSS_CLK>;
@@ -1991,6 +1996,7 @@ 
		reg = <0x7540000 0x1000>;

		cpu = <&CPU5>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm5";



		clocks = <&clock_aop QDSS_CLK>;
@@ -2010,6 +2016,7 @@ 
		reg = <0x7640000 0x1000>;

		cpu = <&CPU6>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm6";



		clocks = <&clock_aop QDSS_CLK>;
@@ -2029,6 +2036,7 @@ 
		reg = <0x7740000 0x1000>;

		cpu = <&CPU7>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm7";



		clocks = <&clock_aop QDSS_CLK>;

arch/arm64/boot/dts/qcom/sm8150-coresight.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -2474,6 +2474,7 @@ 
		reg = <0x7040000 0x1000>;

		cpu = <&CPU0>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm0";



		clocks = <&clock_aop QDSS_CLK>;
@@ -2493,6 +2494,7 @@ 
		reg = <0x7140000 0x1000>;

		cpu = <&CPU1>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm1";



		clocks = <&clock_aop QDSS_CLK>;
@@ -2512,6 +2514,7 @@ 
		reg = <0x7240000 0x1000>;

		cpu = <&CPU2>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm2";



		clocks = <&clock_aop QDSS_CLK>;
@@ -2531,6 +2534,7 @@ 
		reg = <0x7340000 0x1000>;

		cpu = <&CPU3>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm3";



		clocks = <&clock_aop QDSS_CLK>;
@@ -2550,6 +2554,7 @@ 
		reg = <0x7440000 0x1000>;

		cpu = <&CPU4>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm4";



		clocks = <&clock_aop QDSS_CLK>;
@@ -2569,6 +2574,7 @@ 
		reg = <0x7540000 0x1000>;

		cpu = <&CPU5>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm5";



		clocks = <&clock_aop QDSS_CLK>;
@@ -2588,6 +2594,7 @@ 
		reg = <0x7640000 0x1000>;

		cpu = <&CPU6>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm6";



		clocks = <&clock_aop QDSS_CLK>;
@@ -2607,6 +2614,7 @@ 
		reg = <0x7740000 0x1000>;

		cpu = <&CPU7>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm7";



		clocks = <&clock_aop QDSS_CLK>;

drivers/hwtracing/coresight/coresight-etm4x.c

+22 −11
Original line number Diff line number Diff line 
/* Copyright (c) 2014, 2017, The Linux Foundation. All rights reserved.

/* Copyright (c) 2014, 2017-2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -27,6 +27,7 @@ 
#include <linux/cpu.h>

#include <linux/coresight.h>

#include <linux/coresight-pmu.h>

#include <linux/of.h>

#include <linux/pm_wakeup.h>

#include <linux/amba/bus.h>

#include <linux/seq_file.h>
@@ -166,12 +167,14 @@ static void etm4_enable_hw(void *info) 
	writel_relaxed(config->vmid_mask0, drvdata->base + TRCVMIDCCTLR0);

	writel_relaxed(config->vmid_mask1, drvdata->base + TRCVMIDCCTLR1);



	if (!drvdata->tupwr_disable) {

		/*

		 * Request to keep the trace unit powered and also

		 * emulation of powerdown

		 */

	writel_relaxed(readl_relaxed(drvdata->base + TRCPDCR) | TRCPDCR_PU,

		       drvdata->base + TRCPDCR);

		writel_relaxed(readl_relaxed(drvdata->base + TRCPDCR)

				| TRCPDCR_PU, drvdata->base + TRCPDCR);

	}



	/* Enable the trace unit */

	writel_relaxed(1, drvdata->base + TRCPRGCTLR);
@@ -320,10 +323,12 @@ static void etm4_disable_hw(void *info) 


	CS_UNLOCK(drvdata->base);



	if (!drvdata->tupwr_disable) {

		/* power can be removed from the trace unit now */

		control = readl_relaxed(drvdata->base + TRCPDCR);

		control &= ~TRCPDCR_PU;

		writel_relaxed(control, drvdata->base + TRCPDCR);

	}



	control = readl_relaxed(drvdata->base + TRCPRGCTLR);
@@ -1042,6 +1047,12 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) 
	dev_info(dev, "CPU%d: ETM v%d.%d initialized\n",

		 drvdata->cpu, drvdata->arch >> 4, drvdata->arch & 0xf);



	drvdata->tupwr_disable = of_property_read_bool(drvdata->dev->of_node,

				"qcom,tupwr-disable");



	dev_info(dev, "CPU%d: %s initialized\n",

			drvdata->cpu, (char *)id->data);



	if (boot_enable) {

		coresight_enable(drvdata->csdev);

		drvdata->boot_enable = true;

drivers/hwtracing/coresight/coresight-etm4x.h

+3 −1
Original line number Diff line number Diff line 
/* Copyright (c) 2014-2015, 2017, The Linux Foundation. All rights reserved.

/* Copyright (c) 2014-2015, 2017-2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -346,6 +346,7 @@ struct etmv4_config { 
 * @nooverflow:	Indicate if overflow prevention is supported.

 * @atbtrig:	If the implementation can support ATB triggers

 * @lpoverride:	If the implementation can support low-power state over.

 * @tupwr_disable:	If disable the support of keeping trace unit powered.

 * @config:	structure holding configuration parameters.

 */

struct etmv4_drvdata {
@@ -392,6 +393,7 @@ struct etmv4_drvdata { 
	bool				nooverflow;

	bool				atbtrig;

	bool				lpoverride;

	bool				tupwr_disable;

	struct etmv4_config		config;

};