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Commit 32728e2a authored by Mao Jinlong's avatar Mao Jinlong
Browse files

ARM: dts: msm: Add tupwr-disable for SM8150, SM6150 and SDMMAGPIE 



Add property to control power of the trace unit for SM8150, SM6150 and
SDMMAGPIE's ETM. Don't keep trace unit powered across power collapse.

Change-Id: I1d5e71df224b830ebd802652f066991436e4b4e9
Signed-off-by: default avatarMao Jinlong <jinlmao@codeaurora.org>
parent 9e7584b3

arch/arm64/boot/dts/qcom/sdmmagpie-coresight.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -1187,6 +1187,7 @@ 
		reg = <0x7040000 0x1000>;

		cpu = <&CPU0>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm0";



		clocks = <&clock_aop QDSS_CLK>;
@@ -1206,6 +1207,7 @@ 
		reg = <0x7140000 0x1000>;

		cpu = <&CPU1>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm1";



		clocks = <&clock_aop QDSS_CLK>;
@@ -1225,6 +1227,7 @@ 
		reg = <0x7240000 0x1000>;

		cpu = <&CPU2>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm2";



		clocks = <&clock_aop QDSS_CLK>;
@@ -1244,6 +1247,7 @@ 
		reg = <0x7340000 0x1000>;

		cpu = <&CPU3>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm3";



		clocks = <&clock_aop QDSS_CLK>;
@@ -1263,6 +1267,7 @@ 
		reg = <0x7440000 0x1000>;

		cpu = <&CPU4>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm4";



		clocks = <&clock_aop QDSS_CLK>;
@@ -1282,6 +1287,7 @@ 
		reg = <0x7540000 0x1000>;

		cpu = <&CPU5>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm5";



		clocks = <&clock_aop QDSS_CLK>;
@@ -1301,6 +1307,7 @@ 
		reg = <0x7640000 0x1000>;

		cpu = <&CPU6>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm6";



		clocks = <&clock_aop QDSS_CLK>;
@@ -1320,6 +1327,7 @@ 
		reg = <0x7740000 0x1000>;

		cpu = <&CPU7>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm7";



		clocks = <&clock_aop QDSS_CLK>;

arch/arm64/boot/dts/qcom/sm6150-coresight.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -1896,6 +1896,7 @@ 
		reg = <0x7040000 0x1000>;

		cpu = <&CPU0>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm0";



		clocks = <&clock_aop QDSS_CLK>;
@@ -1915,6 +1916,7 @@ 
		reg = <0x7140000 0x1000>;

		cpu = <&CPU1>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm1";



		clocks = <&clock_aop QDSS_CLK>;
@@ -1934,6 +1936,7 @@ 
		reg = <0x7240000 0x1000>;

		cpu = <&CPU2>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm2";



		clocks = <&clock_aop QDSS_CLK>;
@@ -1953,6 +1956,7 @@ 
		reg = <0x7340000 0x1000>;

		cpu = <&CPU3>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm3";



		clocks = <&clock_aop QDSS_CLK>;
@@ -1972,6 +1976,7 @@ 
		reg = <0x7440000 0x1000>;

		cpu = <&CPU4>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm4";



		clocks = <&clock_aop QDSS_CLK>;
@@ -1991,6 +1996,7 @@ 
		reg = <0x7540000 0x1000>;

		cpu = <&CPU5>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm5";



		clocks = <&clock_aop QDSS_CLK>;
@@ -2010,6 +2016,7 @@ 
		reg = <0x7640000 0x1000>;

		cpu = <&CPU6>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm6";



		clocks = <&clock_aop QDSS_CLK>;
@@ -2029,6 +2036,7 @@ 
		reg = <0x7740000 0x1000>;

		cpu = <&CPU7>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm7";



		clocks = <&clock_aop QDSS_CLK>;

arch/arm64/boot/dts/qcom/sm8150-coresight.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -2474,6 +2474,7 @@ 
		reg = <0x7040000 0x1000>;

		cpu = <&CPU0>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm0";



		clocks = <&clock_aop QDSS_CLK>;
@@ -2493,6 +2494,7 @@ 
		reg = <0x7140000 0x1000>;

		cpu = <&CPU1>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm1";



		clocks = <&clock_aop QDSS_CLK>;
@@ -2512,6 +2514,7 @@ 
		reg = <0x7240000 0x1000>;

		cpu = <&CPU2>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm2";



		clocks = <&clock_aop QDSS_CLK>;
@@ -2531,6 +2534,7 @@ 
		reg = <0x7340000 0x1000>;

		cpu = <&CPU3>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm3";



		clocks = <&clock_aop QDSS_CLK>;
@@ -2550,6 +2554,7 @@ 
		reg = <0x7440000 0x1000>;

		cpu = <&CPU4>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm4";



		clocks = <&clock_aop QDSS_CLK>;
@@ -2569,6 +2574,7 @@ 
		reg = <0x7540000 0x1000>;

		cpu = <&CPU5>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm5";



		clocks = <&clock_aop QDSS_CLK>;
@@ -2588,6 +2594,7 @@ 
		reg = <0x7640000 0x1000>;

		cpu = <&CPU6>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm6";



		clocks = <&clock_aop QDSS_CLK>;
@@ -2607,6 +2614,7 @@ 
		reg = <0x7740000 0x1000>;

		cpu = <&CPU7>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm7";



		clocks = <&clock_aop QDSS_CLK>;