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Commit 08fa1a3d authored by Rajkumar Subbiah's avatar Rajkumar Subbiah Committed by Gerrit - the friendly Code Review server
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clk: qcom: Add support for divider flags and table 



The clk-divider module in the clock framework provides support
for different kinds of dividers such as power-of-two and discrete
table based dividers. clk-regmap-divider module which adds regmap
support to the clk-divider doesn't handle the flags and table
parameters in the clk-divider that enables these divider types.
This change adds those two parameters to the clk-regmap-divider
struct and passes them to the clk-divider appropriately.

Change-Id: I0f9a923a62786b19264c45bbcf2400292ed7e61f
Signed-off-by: default avatarRajkumar Subbiah <rsubbia@codeaurora.org>
parent 3008f900

drivers/clk/qcom/clk-regmap-divider.c

+10 −7
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2014, The Linux Foundation. All rights reserved.

 * Copyright (c) 2014, 2017, The Linux Foundation. All rights reserved.

 *

 * This software is licensed under the terms of the GNU General Public

 * License version 2, as published by the Free Software Foundation, and
@@ -28,8 +28,10 @@ static long div_round_rate(struct clk_hw *hw, unsigned long rate, 
{

	struct clk_regmap_div *divider = to_clk_regmap_div(hw);



	return divider_round_rate(hw, rate, prate, NULL, divider->width,

				  CLK_DIVIDER_ROUND_CLOSEST);

	return divider_round_rate(hw, rate, prate, divider->table,

				  divider->width,

				  CLK_DIVIDER_ROUND_CLOSEST |

				  divider->flags);

}



static int div_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -39,8 +41,9 @@ static int div_set_rate(struct clk_hw *hw, unsigned long rate, 
	struct clk_regmap *clkr = &divider->clkr;

	u32 div;



	div = divider_get_val(rate, parent_rate, NULL, divider->width,

			      CLK_DIVIDER_ROUND_CLOSEST);

	div = divider_get_val(rate, parent_rate, divider->table,

			      divider->width, CLK_DIVIDER_ROUND_CLOSEST |

			      divider->flags);



	return regmap_update_bits(clkr->regmap, divider->reg,

				  (BIT(divider->width) - 1) << divider->shift,
@@ -58,8 +61,8 @@ static unsigned long div_recalc_rate(struct clk_hw *hw, 
	div >>= divider->shift;

	div &= BIT(divider->width) - 1;



	return divider_recalc_rate(hw, parent_rate, div, NULL,

				   CLK_DIVIDER_ROUND_CLOSEST);

	return divider_recalc_rate(hw, parent_rate, div, divider->table,

				   CLK_DIVIDER_ROUND_CLOSEST | divider->flags);

}



const struct clk_ops clk_regmap_div_ops = {

drivers/clk/qcom/clk-regmap-divider.h

+7 −5
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2014, The Linux Foundation. All rights reserved.

 * Copyright (c) 2014, 2017, The Linux Foundation. All rights reserved.

 *

 * This software is licensed under the terms of the GNU General Public

 * License version 2, as published by the Free Software Foundation, and
@@ -21,6 +21,8 @@ struct clk_regmap_div { 
	u32				reg;

	u32				shift;

	u32				width;

	u32				flags;

	const struct clk_div_table	*table;

	struct clk_regmap		clkr;

};