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Commit 06d0f066 authored by Sujith's avatar Sujith Committed by John W. Linville
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ath9k: Enable Fractional N mode



This patch enables Fractional N mode for all channel
if the EEPROM says so, and also fixes the INI only
when the device is not a 2 GHz only capable device.

Signed-off-by: default avatarSujith <Sujith.Manoharan@atheros.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent fec0de11
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+7 −0
Original line number Diff line number Diff line
@@ -466,6 +466,8 @@ static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
		return pBase->txMask;
	case EEP_RX_MASK:
		return pBase->rxMask;
	case EEP_FRAC_N_5G:
		return 0;
	default:
		return 0;
	}
@@ -1599,6 +1601,11 @@ static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
			return pBase->dacHiPwrMode_5G;
		else
			return 0;
	case EEP_FRAC_N_5G:
		if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_22)
			return pBase->frac_n_5g;
		else
			return 0;
	default:
		return 0;
	}
+5 −1
Original line number Diff line number Diff line
@@ -125,6 +125,7 @@
#define AR5416_EEP_MINOR_VER_17      0x11
#define AR5416_EEP_MINOR_VER_19      0x13
#define AR5416_EEP_MINOR_VER_20      0x14
#define AR5416_EEP_MINOR_VER_22      0x16

#define AR5416_NUM_5G_CAL_PIERS         8
#define AR5416_NUM_2G_CAL_PIERS         4
@@ -188,6 +189,7 @@ enum eeprom_param {
	EEP_RXGAIN_TYPE,
	EEP_TXGAIN_TYPE,
	EEP_DAC_HPWR_5G,
	EEP_FRAC_N_5G
};

enum ar5416_rates {
@@ -232,7 +234,9 @@ struct base_eep_header {
	u8 txGainType;
	u8 rcChainMask;
	u8 desiredScaleCCK;
	u8 futureBase_3[23];
	u8 power_table_offset;
	u8 frac_n_5g;
	u8 futureBase_3[21];
} __packed;

struct base_eep_header_4k {
+10 −8
Original line number Diff line number Diff line
@@ -823,7 +823,16 @@ static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
	if (AR_SREV_9280_20(ah))
		ath9k_hw_init_txgain_ini(ah);

	if (ah->hw_version.devid == AR9280_DEVID_PCI) {
	if (!ath9k_hw_fill_cap_info(ah)) {
		DPRINTF(sc, ATH_DBG_RESET, "failed ath9k_hw_fill_cap_info\n");
		ecode = -EINVAL;
		goto bad;
	}

	if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
	    test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {

		/* EEPROM Fixup */
		for (i = 0; i < ah->iniModes.ia_rows; i++) {
			u32 reg = INI_RA(&ah->iniModes, i, 0);

@@ -838,13 +847,6 @@ static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
		}
	}

	if (!ath9k_hw_fill_cap_info(ah)) {
		DPRINTF(sc, ATH_DBG_RESET,
			"failed ath9k_hw_fill_cap_info\n");
		ecode = -EINVAL;
		goto bad;
	}

	ecode = ath9k_hw_init_macaddr(ah);
	if (ecode != 0) {
		DPRINTF(sc, ATH_DBG_RESET,
+13 −6
Original line number Diff line number Diff line
@@ -132,20 +132,27 @@ ath9k_hw_ar9280_set_channel(struct ath_hw *ah,
		bMode = 0;
		fracMode = 0;

		switch(ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) {
		case 0:
			if ((freq % 20) == 0) {
				aModeRefSel = 3;
			} else if ((freq % 10) == 0) {
				aModeRefSel = 2;
		} else {
			}
			if (aModeRefSel)
				break;
		case 1:
		default:
			aModeRefSel = 0;

			fracMode = 1;
			refDivA = 1;
			channelSel = (freq * 0x8000) / 15;

			REG_RMW_FIELD(ah, AR_AN_SYNTH9,
				      AR_AN_SYNTH9_REFDIVA, refDivA);

		}

		if (!fracMode) {
			ndiv = (freq * (refDivA >> aModeRefSel)) / 60;
			channelSel = ndiv & 0x1ff;