usb: dwc3: gadget: Prevent core from processing stale TRBs

With CPU re-ordering on write instructions, there might
be a chance that the HWO is set before the TRB is updated
with the new mapped buffer address.
And in the case where core is processing a list of TRBs
it is possible that it fetched the TRBs when the HWO is set
but before the buffer address is updated.
Prevent this by adding a memory barrier before the HWO
is updated to ensure that the core always process the
updated TRBs.

Change-Id: Idc008b2d4e37dd0c10c8ae40ab5af1ffd0775877
Signed-off-by: Sriharsha Allenki <sallenki@codeaurora.org>