Merge "clk: qcom: debugcc-sm8150: Add mccc_debug node" (04019b5c) · Commits · e / devices / android_kernel_oneplus_sm8150

Documentation/devicetree/bindings/clock/qcom,debugcc.txt

+2 −0

Original line number	Diff line number	Diff line
		@@ -11,6 +11,7 @@ Required properties :
		- qcom,dispcc: phandle to the Display CC device node.
		- qcom,npucc: phandle to the NPU CC device node.
		- qcom,cpucc: phandle to the CPU CC debug device node.
		- qcom,mccc: phandle to the MC CC debug device node.
		- clock-names: Shall contain "xo_clk_src"
		- clocks: phandle + clock reference to the CXO clock.
		- #clock-cells : Shall contain 1.
		@@ -24,6 +25,7 @@ Example:
		qcom,dispcc = <&clock_dispcc>;
		qcom,npucc = <&clock_npucc>;
		qcom,cpucc = <&cpucc_debug>;
		qcom,mccc = <&mccc_debug>;
		clock-names = "xo_clk_src";
		clocks = <&clock_rpmh RPMH_CXO_CLK>;
		#clock-cells = <1>;

arch/arm64/boot/dts/qcom/sm8150.dtsi

+6 −0

Original line number	Diff line number	Diff line
		@@ -1466,6 +1466,11 @@
		reg = <0x182a0018 0x4>;
		};

		mccc_debug: syscon@90b0000 {
		compatible = "syscon";
		reg = <0x90b0000 0x1000>;
		};

		clock_cpucc: qcom,cpucc {
		compatible = "qcom,clk-cpu-osm";
		reg = <0x18321000 0x1400>,
		@@ -1489,6 +1494,7 @@
		qcom,npucc = <&clock_npucc>;
		qcom,gpucc = <&clock_gpucc>;
		qcom,cpucc = <&cpucc_debug>;
		qcom,mccc = <&mccc_debug>;
		clock-names = "xo_clk_src";
		clocks = <&clock_rpmh RPMH_CXO_CLK>;
		#clock-cells = <1>;

drivers/clk/qcom/clk-debug.c

+45 −1

Original line number	Diff line number	Diff line
		@@ -297,15 +297,54 @@ static int clk_debug_measure_get(void data, u64 val)
		DEFINE_SIMPLE_ATTRIBUTE(clk_measure_fops, clk_debug_measure_get,
		NULL, "%lld\n");

		static int clk_debug_read_period(void data, u64 val)
		{
		struct clk_hw *hw = data;
		struct clk_debug_mux *meas = to_clk_measure(measure);
		int index;
		int dbg_cc;
		int ret = 0;
		u32 regval;

		mutex_lock(&clk_debug_lock);

		ret = clk_set_parent(measure->clk, hw->clk);
		if (!ret) {
		index = clk_debug_mux_get_parent(measure);
		dbg_cc = meas->parent[index].dbg_cc;

		regmap_read(meas->regmap[dbg_cc], meas->period_offset, &regval);
		if (!regval) {
		pr_err("Error reading mccc period register, ret = %d\n",
		ret);
		mutex_unlock(&clk_debug_lock);
		return 0;
		}
		*val = 1000000000000UL;
		do_div(*val, regval);
		} else {
		pr_err("Failed to set the debug mux's parent.\n");
		}

		mutex_unlock(&clk_debug_lock);
		return ret;
		}

		DEFINE_SIMPLE_ATTRIBUTE(clk_read_period_fops, clk_debug_read_period,
		NULL, "%lld\n");

		int clk_debug_measure_add(struct clk_hw hw, struct dentry dentry)
		{
		int ret;
		int index;
		struct clk_debug_mux *meas;

		if (IS_ERR_OR_NULL(measure)) {
		pr_err_once("Please check if `measure` clk is registered.\n");
		return 0;
		}

		meas = to_clk_measure(measure);
		ret = clk_set_parent(measure->clk, hw->clk);
		if (ret) {
		pr_debug("Unable to set %s as %s's parent, ret=%d\n",
		@@ -313,6 +352,11 @@ int clk_debug_measure_add(struct clk_hw hw, struct dentry dentry)
		return 0;
		}

		index = clk_debug_mux_get_parent(measure);
		if (meas->parent[index].dbg_cc == MC_CC)
		debugfs_create_file("clk_measure", 0444, dentry, hw,
		&clk_read_period_fops);
		else
		debugfs_create_file("clk_measure", 0444, dentry, hw,
		&clk_measure_fops);
		return 0;

drivers/clk/qcom/clk-debug.h

+4 −0

Original line number	Diff line number	Diff line
		@@ -45,6 +45,7 @@ enum debug_cc {
		GPU_CC,
		VIDEO_CC,
		CPU_CC,
		MC_CC,
		MAX_NUM_CC,
		};

		@@ -111,6 +112,8 @@ struct clk_src {
		mux.
		* @post_div_shift: indicates the shift required for post divider
		selection in primary mux.
		* @period_offset: offset of the period register used to read to determine
		the mc clock period
		* @hw: handle between common and hardware-specific interfaces.
		*/
		struct clk_debug_mux {
		@@ -126,6 +129,7 @@ struct clk_debug_mux {
		u32 src_sel_shift;
		u32 post_div_mask;
		u32 post_div_shift;
		u32 period_offset;
		struct clk_hw hw;
		};

drivers/clk/qcom/debugcc-sm8150.c

+7 −2

Original line number	Diff line number	Diff line
		@@ -120,7 +120,7 @@ static const char *const debug_mux_parent_names[] = {
		"disp_cc_xo_clk",
		"measure_only_snoc_clk",
		"measure_only_cnoc_clk",
		"measure_only_bimc_clk",
		"measure_only_mccc_clk",
		"measure_only_ipa_2x_clk",
		"gcc_aggre_noc_pcie_tbu_clk",
		"gcc_aggre_ufs_card_axi_clk",
		@@ -293,6 +293,7 @@ static struct clk_debug_mux gcc_debug_mux = {
		.src_sel_shift = 0,
		.post_div_mask = 0xF,
		.post_div_shift = 0,
		.period_offset = 0x50,
		MUX_SRC_LIST(
		{ "cam_cc_bps_ahb_clk", 0x55, 1, CAM_CC,
		0xE, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 },
		@@ -468,7 +469,7 @@ static struct clk_debug_mux gcc_debug_mux = {
		0x7, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x62004, 0x62008 },
		{ "measure_only_cnoc_clk", 0x19, 1, GCC,
		0x19, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x62004, 0x62008 },
		{ "measure_only_bimc_clk", 0xD0, 1, GCC,
		{ "measure_only_mccc_clk", 0xD0, 1, MC_CC,
		0xD0, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x62004, 0x62008 },
		{ "measure_only_ipa_2x_clk", 0x147, 1, GCC,
		0x147, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x62004, 0x62008 },
		@@ -870,6 +871,10 @@ static int clk_debug_sm8150_probe(struct platform_device *pdev)
		if (ret)
		return ret;

		ret = map_debug_bases(pdev, "qcom,mccc", MC_CC);
		if (ret)
		return ret;

		clk = devm_clk_register(&pdev->dev, &gcc_debug_mux.hw);
		if (IS_ERR(clk)) {
		dev_err(&pdev->dev, "Unable to register GCC debug mux\n");