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Commit f45dbc84 authored by David Dai's avatar David Dai
Browse files

clk: qcom: debugcc-sm8150: Add mccc_debug node



Change the name of the measure_only_bimc_clk to better reflect
the name of the clock(memory controller clock controller) we're trying to
measure as bimc(bus integrated memory controller) no longer exists.
Add an additional MC_CC debug base and dt binding in order to map the
mc clock period register used to calculate the frequency of the MC clock.

Change-Id: Iede4ea25c140fc5937f06175341f978c792a42a5
Signed-off-by: default avatarDavid Dai <daidavid1@codeaurora.org>
parent 5725b8db
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+2 −0
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ Required properties :
- qcom,dispcc: phandle to the Display CC device node.
- qcom,npucc: phandle to the NPU CC device node.
- qcom,cpucc: phandle to the CPU CC debug device node.
- qcom,mccc: phandle to the MC CC debug device node.
- clock-names: Shall contain "xo_clk_src"
- clocks: phandle + clock reference to the CXO clock.
- #clock-cells : Shall contain 1.
@@ -24,6 +25,7 @@ Example:
		qcom,dispcc = <&clock_dispcc>;
		qcom,npucc = <&clock_npucc>;
		qcom,cpucc = <&cpucc_debug>;
		qcom,mccc = <&mccc_debug>;
		clock-names = "xo_clk_src";
		clocks = <&clock_rpmh RPMH_CXO_CLK>;
		#clock-cells = <1>;
+6 −0
Original line number Diff line number Diff line
@@ -1466,6 +1466,11 @@
		reg = <0x182a0018 0x4>;
	};

	mccc_debug: syscon@90b0000 {
		compatible = "syscon";
		reg = <0x90b0000 0x1000>;
	};

	clock_cpucc: qcom,cpucc {
		compatible = "qcom,clk-cpu-osm";
		reg = <0x18321000 0x1400>,
@@ -1489,6 +1494,7 @@
		qcom,npucc = <&clock_npucc>;
		qcom,gpucc = <&clock_gpucc>;
		qcom,cpucc = <&cpucc_debug>;
		qcom,mccc = <&mccc_debug>;
		clock-names = "xo_clk_src";
		clocks = <&clock_rpmh RPMH_CXO_CLK>;
		#clock-cells = <1>;
+7 −2
Original line number Diff line number Diff line
@@ -120,7 +120,7 @@ static const char *const debug_mux_parent_names[] = {
	"disp_cc_xo_clk",
	"measure_only_snoc_clk",
	"measure_only_cnoc_clk",
	"measure_only_bimc_clk",
	"measure_only_mccc_clk",
	"measure_only_ipa_2x_clk",
	"gcc_aggre_noc_pcie_tbu_clk",
	"gcc_aggre_ufs_card_axi_clk",
@@ -293,6 +293,7 @@ static struct clk_debug_mux gcc_debug_mux = {
	.src_sel_shift = 0,
	.post_div_mask = 0xF,
	.post_div_shift = 0,
	.period_offset = 0x50,
	MUX_SRC_LIST(
		{ "cam_cc_bps_ahb_clk", 0x55, 1, CAM_CC,
			0xE, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 },
@@ -468,7 +469,7 @@ static struct clk_debug_mux gcc_debug_mux = {
			0x7, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x62004, 0x62008 },
		{ "measure_only_cnoc_clk", 0x19, 1, GCC,
			0x19, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x62004, 0x62008 },
		{ "measure_only_bimc_clk", 0xD0, 1, GCC,
		{ "measure_only_mccc_clk", 0xD0, 1, MC_CC,
			0xD0, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x62004, 0x62008 },
		{ "measure_only_ipa_2x_clk", 0x147, 1, GCC,
			0x147, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x62004, 0x62008 },
@@ -870,6 +871,10 @@ static int clk_debug_sm8150_probe(struct platform_device *pdev)
	if (ret)
		return ret;

	ret = map_debug_bases(pdev, "qcom,mccc", MC_CC);
	if (ret)
		return ret;

	clk = devm_clk_register(&pdev->dev, &gcc_debug_mux.hw);
	if (IS_ERR(clk)) {
		dev_err(&pdev->dev, "Unable to register GCC debug mux\n");
+3 −3
Original line number Diff line number Diff line
@@ -193,10 +193,10 @@ static struct clk_dummy measure_only_cnoc_clk = {
	},
};

static struct clk_dummy measure_only_bimc_clk = {
static struct clk_dummy measure_only_mccc_clk = {
	.rrate = 1000,
	.hw.init = &(struct clk_init_data){
		.name = "measure_only_bimc_clk",
		.name = "measure_only_mccc_clk",
		.ops = &clk_dummy_ops,
	},
};
@@ -3901,7 +3901,7 @@ static struct clk_branch gcc_video_xo_clk = {
struct clk_hw *gcc_sm8150_hws[] = {
	[MEASURE_ONLY_SNOC_CLK] = &measure_only_snoc_clk.hw,
	[MEASURE_ONLY_CNOC_CLK] = &measure_only_cnoc_clk.hw,
	[MEASURE_ONLY_BIMC_CLK] = &measure_only_bimc_clk.hw,
	[MEASURE_ONLY_MCCC_CLK] = &measure_only_mccc_clk.hw,
	[MEASURE_ONLY_IPA_2X_CLK] = &measure_only_ipa_2x_clk.hw,
	[MMCX_CLK] = &mmcx_clk.hw,
};
+1 −1
Original line number Diff line number Diff line
@@ -251,7 +251,7 @@
/* Dummy clocks for rate measurement */
#define MEASURE_ONLY_SNOC_CLK					0
#define MEASURE_ONLY_CNOC_CLK					1
#define MEASURE_ONLY_BIMC_CLK					2
#define MEASURE_ONLY_MCCC_CLK					2
#define MEASURE_ONLY_IPA_2X_CLK					3
#define MMCX_CLK						4