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Commit 034fee39 authored by Shefali Jain's avatar Shefali Jain
Browse files

clk: qcom: gcc-qcs405: Add support for bias pll clock 



Add support for misc_reset, ahb and aon clock.

Change-Id: I4f105fcfaed3a83078a350897b55e41748c8f44a
Signed-off-by: default avatarShefali Jain <shefjain@codeaurora.org>
parent 8f765160

drivers/clk/qcom/gcc-qcs405.c

+45 −1
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2018, The Linux Foundation. All rights reserved.

 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -1401,6 +1401,46 @@ static struct clk_rcg2 vsync_clk_src = { 
	},

};



static struct clk_branch gcc_bias_pll_misc_reset_clk  = {

	.halt_reg = 0x3c004,

	.halt_check = BRANCH_HALT_SKIP,

	.clkr = {

		.enable_reg = 0x3c004,

		.enable_is_inverted = true,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_bias_pll_misc_reset_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_bias_pll_ahb_clk = {

	.halt_reg = 0x3c008,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x3c008,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_bias_pll_ahb_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_bias_pll_aon_clk = {

	.halt_reg = 0x3c00c,

	.halt_check = BRANCH_HALT_DELAY,

	.clkr = {

		.enable_reg = 0x3c00c,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_bias_pll_aon_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_apss_ahb_clk = {

	.halt_reg = 0x4601c,

	.halt_check = BRANCH_HALT_VOTED,
@@ -2847,6 +2887,9 @@ static struct clk_regmap *gcc_qcs405_clocks[] = { 
	[GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,

	[GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,

	[GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,

	[GCC_BIAS_PLL_MISC_RESET_CLK] = &gcc_bias_pll_misc_reset_clk.clkr,

	[GCC_BIAS_PLL_AHB_CLK] = &gcc_bias_pll_ahb_clk.clkr,

	[GCC_BIAS_PLL_AON_CLK] = &gcc_bias_pll_aon_clk.clkr,

};



static const struct qcom_reset_map gcc_qcs405_resets[] = {
@@ -2864,6 +2907,7 @@ static const struct qcom_reset_map gcc_qcs405_resets[] = { 
	[GCC_PCIE_0_LINK_DOWN_BCR] = {0x3E038},

	[GCC_PCIEPHY_0_PHY_BCR] = {0x3E03C},

	[GCC_EMAC_BCR] = {0x4E000},

	[GCC_BIAS_PLL_BCR] = {0x3C000},

};



static const struct regmap_config gcc_qcs405_regmap_config = {

include/dt-bindings/clock/qcom,gcc-qcs405.h

+5 −1
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2018, The Linux Foundation. All rights reserved.

 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -153,6 +153,9 @@ 
#define GCC_CRYPTO_CLK					137

#define GCC_MDP_TBU_CLK					138

#define GCC_QDSS_DAP_CLK				139

#define GCC_BIAS_PLL_MISC_RESET_CLK			142

#define GCC_BIAS_PLL_AHB_CLK				143

#define GCC_BIAS_PLL_AON_CLK				144



#define GCC_GENI_IR_BCR					0

#define GCC_USB_HS_BCR					1
@@ -168,5 +171,6 @@ 
#define GCC_PCIE_0_LINK_DOWN_BCR			11

#define GCC_PCIEPHY_0_PHY_BCR				12

#define GCC_EMAC_BCR					13

#define GCC_BIAS_PLL_BCR				14



#endif