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Commit 00f0427d authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "clk: qcom: debugcc-sm8150: Add measurement support for CPU clocks on SM8150"

parents 7bd0bce3 d40c391c

Documentation/devicetree/bindings/clock/qcom,debugcc.txt

+2 −0
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ Required properties : 
- qcom,camcc: phandle to the Camera CC device node.

- qcom,dispcc: phandle to the Display CC device node.

- qcom,npucc: phandle to the NPU CC device node.

- qcom,cpucc: phandle to the CPU CC debug device node.

- clock-names: Shall contain "xo_clk_src"

- clocks: phandle + clock reference to the CXO clock.

- #clock-cells : Shall contain 1.
@@ -21,6 +22,7 @@ Example: 
		qcom,camcc = <&clock_camcc>;

		qcom,dispcc = <&clock_dispcc>;

		qcom,npucc = <&clock_npucc>;

		qcom,cpucc = <&cpucc_debug>;

		clock-names = "xo_clk_src";

		clocks = <&clock_rpmh RPMH_CXO_CLK>;

		#clock-cells = <1>;

arch/arm64/boot/dts/qcom/sm8150.dtsi

+6 −0
Original line number Diff line number Diff line
@@ -1421,6 +1421,11 @@ 
		#reset-cells = <1>;

	};



	cpucc_debug: syscon@182a0018 {

		compatible = "syscon";

		reg = <0x182a0018 0x4>;

	};



	clock_cpucc: qcom,cpucc {

		compatible = "qcom,clk-cpu-osm";

		reg = <0x18321000 0x1400>,
@@ -1442,6 +1447,7 @@ 
		qcom,dispcc = <&clock_dispcc>;

		qcom,npucc = <&clock_npucc>;

		qcom,gpucc = <&clock_gpucc>;

		qcom,cpucc = <&cpucc_debug>;

		clock-names = "xo_clk_src";

		clocks = <&clock_rpmh RPMH_CXO_CLK>;

		#clock-cells = <1>;

drivers/clk/qcom/clk-cpu-osm.c

+3 −0
Original line number Diff line number Diff line
@@ -36,6 +36,7 @@ 
#include "common.h"

#include "clk-regmap.h"

#include "clk-voter.h"

#include "clk-debug.h"



#define OSM_INIT_RATE			300000000UL

#define XO_RATE				19200000UL
@@ -169,6 +170,7 @@ static int clk_osm_search_table(struct osm_entry *table, int entries, long rate) 
const struct clk_ops clk_ops_cpu_osm = {

	.round_rate = clk_osm_round_rate,

	.list_rate = clk_osm_list_rate,

	.debug_init = clk_debug_measure_add,

};



static int clk_core_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -264,6 +266,7 @@ const static struct clk_ops clk_ops_l3_osm = { 
	.list_rate = clk_osm_list_rate,

	.recalc_rate = l3_clk_recalc_rate,

	.set_rate = l3_clk_set_rate,

	.debug_init = clk_debug_measure_add,

};



static struct clk_init_data osm_clks_init[] = {

drivers/clk/qcom/debugcc-sm8150.c

+16 −0
Original line number Diff line number Diff line
@@ -278,6 +278,10 @@ static const char *const debug_mux_parent_names[] = { 
	"video_cc_mvs1_core_clk",

	"video_cc_mvsc_core_clk",

	"video_cc_xo_clk",

	"l3_clk",

	"pwrcl_clk",

	"perfcl_clk",

	"perfpcl_clk"

};



static struct clk_debug_mux gcc_debug_mux = {
@@ -780,6 +784,14 @@ static struct clk_debug_mux gcc_debug_mux = { 
			0x1, 0x3F, 0, 0x7, 0, 5, 0xA4C, 0x938, 0x940 },

		{ "video_cc_xo_clk", 0x57, 1, VIDEO_CC,

			0x8, 0x3F, 0, 0x7, 0, 5, 0xA4C, 0x938, 0x940 },

		{ "l3_clk", 0xE8, 4, CPU_CC,

			0x46, 0x7F, 4, 0xf, 11, 1, 0x0, 0x0, U32_MAX, 16 },

		{ "pwrcl_clk", 0xE8, 4, CPU_CC,

			0x44, 0x7F, 4, 0xf, 11, 1, 0x0, 0x0, U32_MAX, 16 },

		{ "perfcl_clk", 0xE8, 4, CPU_CC,

			0x45, 0x7F, 4, 0xf, 11, 1, 0x0, 0x0, U32_MAX, 16 },

		{ "perfpcl_clk", 0xE8, 4, CPU_CC,

			0x47, 0x7F, 4, 0xf, 11, 1, 0x0, 0x0, U32_MAX, 16 },

	),

	.hw.init = &(struct clk_init_data){

		.name = "gcc_debug_mux",
@@ -854,6 +866,10 @@ static int clk_debug_sm8150_probe(struct platform_device *pdev) 
	if (ret)

		return ret;



	ret = map_debug_bases(pdev, "qcom,cpucc", CPU_CC);

	if (ret)

		return ret;



	clk = devm_clk_register(&pdev->dev, &gcc_debug_mux.hw);

	if (IS_ERR(clk)) {

		dev_err(&pdev->dev, "Unable to register GCC debug mux\n");