Loading arch/arm64/boot/dts/qcom/sm8150-sde.dtsi +0 −2 Original line number Diff line number Diff line Loading @@ -313,7 +313,6 @@ qcom,msm-bus,name = "mdss_reg"; qcom,msm-bus,num-cases = <4>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,active-only; qcom,msm-bus,vectors-KBps = <1 590 0 0>, <1 590 0 76800>, Loading Loading @@ -457,7 +456,6 @@ qcom,msm-bus,name = "mdss_rot_reg"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,active-only; qcom,msm-bus,vectors-KBps = <1 590 0 0>, <1 590 0 76800>; Loading drivers/gpu/drm/msm/dp/dp_ctrl.c +9 −3 Original line number Diff line number Diff line Loading @@ -759,12 +759,16 @@ static void dp_ctrl_process_phy_test_request(struct dp_ctrl *dp_ctrl) * link clocks and core clocks. */ ctrl->dp_ctrl.reset(&ctrl->dp_ctrl); ctrl->dp_ctrl.stream_off(&ctrl->dp_ctrl, ctrl->panel); ctrl->dp_ctrl.off(&ctrl->dp_ctrl); ctrl->aux->init(ctrl->aux, ctrl->parser->aux_cfg); ret = ctrl->dp_ctrl.on(&ctrl->dp_ctrl, ctrl->mst_mode); if (ret) pr_err("failed to enable DP controller\n"); ctrl->dp_ctrl.stream_on(&ctrl->dp_ctrl, ctrl->panel); pr_debug("end\n"); } Loading Loading @@ -905,6 +909,11 @@ static int dp_ctrl_stream_on(struct dp_ctrl *dp_ctrl, struct dp_panel *panel) goto end; } if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) { dp_ctrl_send_phy_test_pattern(ctrl); return 0; } rc = dp_ctrl_mst_stream_setup(ctrl, panel); if (rc) goto end; Loading Loading @@ -991,9 +1000,6 @@ static int dp_ctrl_on(struct dp_ctrl *dp_ctrl, bool mst_mode) dp_ctrl_enable_mainlink_clocks(ctrl); } if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) dp_ctrl_send_phy_test_pattern(ctrl); ctrl->power_on = true; pr_debug("End-\n"); Loading drivers/gpu/drm/msm/sde/sde_hw_catalog.c +14 −4 Original line number Diff line number Diff line Loading @@ -3522,16 +3522,20 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) rc = sde_hardware_format_caps(sde_cfg, hw_rev); if (IS_MSM8996_TARGET(hw_rev)) { /* update msm8996 target here */ sde_cfg->perf.min_prefill_lines = 21; } else if (IS_MSM8998_TARGET(hw_rev)) { /* update msm8998 target here */ sde_cfg->has_wb_ubwc = true; sde_cfg->perf.min_prefill_lines = 25; sde_cfg->vbif_qos_nlvl = 4; sde_cfg->ts_prefill_rev = 1; } else if (IS_SDM845_TARGET(hw_rev) || IS_SDM670_TARGET(hw_rev)) { /* update sdm845 target here */ } else if (IS_SDM845_TARGET(hw_rev)) { sde_cfg->has_wb_ubwc = true; sde_cfg->perf.min_prefill_lines = 24; sde_cfg->vbif_qos_nlvl = 8; sde_cfg->ts_prefill_rev = 2; sde_cfg->sui_misr_supported = true; sde_cfg->sui_block_xin_mask = 0x3F71; } else if (IS_SDM670_TARGET(hw_rev)) { sde_cfg->has_wb_ubwc = true; sde_cfg->perf.min_prefill_lines = 24; sde_cfg->vbif_qos_nlvl = 8; Loading @@ -3544,6 +3548,8 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0; sde_cfg->delay_prg_fetch_start = true; sde_cfg->sui_ns_allowed = true; sde_cfg->sui_misr_supported = true; sde_cfg->sui_block_xin_mask = 0x3F71; } else if (IS_SDMSHRIKE_TARGET(hw_rev)) { sde_cfg->has_wb_ubwc = true; sde_cfg->perf.min_prefill_lines = 24; Loading @@ -3569,6 +3575,10 @@ static int _sde_hardware_post_caps(struct sde_mdss_cfg *sde_cfg, if (!sde_cfg) return -EINVAL; if (IS_SM8150_TARGET(hw_rev)) sde_cfg->sui_supported_blendstage = sde_cfg->max_mixer_blendstages - SDE_STAGE_0; for (i = 0; i < sde_cfg->sspp_count; i++) { if (sde_cfg->sspp[i].sblk) { max_horz_deci = max(max_horz_deci, Loading drivers/gpu/drm/msm/sde/sde_rm.c +1 −1 Original line number Diff line number Diff line Loading @@ -1211,7 +1211,7 @@ static u32 _sde_rm_poll_intr_status_for_cont_splash(struct sde_hw_intr *intr, } SDE_EVT32(status, irq_idx_pp_done, SDE_EVTLOG_ERROR); SDE_ERROR("polling timed out. status = 0x%x\n", status); SDE_DEBUG("polling timed out. status = 0x%x\n", status); return -ETIMEDOUT; } Loading drivers/gpu/drm/msm/sde_io_util.c +24 −1 Original line number Diff line number Diff line /* Copyright (c) 2012-2015, 2017, The Linux Foundation. All rights reserved. /* Copyright (c) 2012-2015, 2017-2018 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and Loading Loading @@ -217,6 +217,7 @@ int msm_dss_enable_vreg(struct dss_vreg *in_vreg, int num_vreg, int enable) { int i = 0, rc = 0; bool need_sleep; int reg_mode; if (enable) { for (i = 0; i < num_vreg; i++) { Loading @@ -227,6 +228,17 @@ int msm_dss_enable_vreg(struct dss_vreg *in_vreg, int num_vreg, int enable) in_vreg[i].vreg_name, rc); goto vreg_set_opt_mode_fail; } reg_mode = regulator_get_mode(in_vreg[i].vreg); if (reg_mode == REGULATOR_MODE_FAST) { DEV_DBG("%pS->%s: %s operation not allowed\n", __builtin_return_address(0), __func__, in_vreg[i].vreg_name); /* * This regulator is controlled by Hw cannot be * controlled by Sw vote */ continue; } need_sleep = !regulator_is_enabled(in_vreg[i].vreg); if (in_vreg[i].pre_on_sleep && need_sleep) usleep_range(in_vreg[i].pre_on_sleep * 1000, Loading @@ -252,6 +264,17 @@ int msm_dss_enable_vreg(struct dss_vreg *in_vreg, int num_vreg, int enable) } } else { for (i = num_vreg-1; i >= 0; i--) { reg_mode = regulator_get_mode(in_vreg[i].vreg); if (reg_mode == REGULATOR_MODE_FAST) { DEV_DBG("%pS->%s: %s operation not allowed\n", __builtin_return_address(0), __func__, in_vreg[i].vreg_name); /* * This regulator is controlled by Hw cannot be * controlled by Sw vote */ continue; } if (in_vreg[i].pre_off_sleep) usleep_range(in_vreg[i].pre_off_sleep * 1000, in_vreg[i].pre_off_sleep * 1000); Loading Loading
arch/arm64/boot/dts/qcom/sm8150-sde.dtsi +0 −2 Original line number Diff line number Diff line Loading @@ -313,7 +313,6 @@ qcom,msm-bus,name = "mdss_reg"; qcom,msm-bus,num-cases = <4>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,active-only; qcom,msm-bus,vectors-KBps = <1 590 0 0>, <1 590 0 76800>, Loading Loading @@ -457,7 +456,6 @@ qcom,msm-bus,name = "mdss_rot_reg"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,active-only; qcom,msm-bus,vectors-KBps = <1 590 0 0>, <1 590 0 76800>; Loading
drivers/gpu/drm/msm/dp/dp_ctrl.c +9 −3 Original line number Diff line number Diff line Loading @@ -759,12 +759,16 @@ static void dp_ctrl_process_phy_test_request(struct dp_ctrl *dp_ctrl) * link clocks and core clocks. */ ctrl->dp_ctrl.reset(&ctrl->dp_ctrl); ctrl->dp_ctrl.stream_off(&ctrl->dp_ctrl, ctrl->panel); ctrl->dp_ctrl.off(&ctrl->dp_ctrl); ctrl->aux->init(ctrl->aux, ctrl->parser->aux_cfg); ret = ctrl->dp_ctrl.on(&ctrl->dp_ctrl, ctrl->mst_mode); if (ret) pr_err("failed to enable DP controller\n"); ctrl->dp_ctrl.stream_on(&ctrl->dp_ctrl, ctrl->panel); pr_debug("end\n"); } Loading Loading @@ -905,6 +909,11 @@ static int dp_ctrl_stream_on(struct dp_ctrl *dp_ctrl, struct dp_panel *panel) goto end; } if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) { dp_ctrl_send_phy_test_pattern(ctrl); return 0; } rc = dp_ctrl_mst_stream_setup(ctrl, panel); if (rc) goto end; Loading Loading @@ -991,9 +1000,6 @@ static int dp_ctrl_on(struct dp_ctrl *dp_ctrl, bool mst_mode) dp_ctrl_enable_mainlink_clocks(ctrl); } if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) dp_ctrl_send_phy_test_pattern(ctrl); ctrl->power_on = true; pr_debug("End-\n"); Loading
drivers/gpu/drm/msm/sde/sde_hw_catalog.c +14 −4 Original line number Diff line number Diff line Loading @@ -3522,16 +3522,20 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) rc = sde_hardware_format_caps(sde_cfg, hw_rev); if (IS_MSM8996_TARGET(hw_rev)) { /* update msm8996 target here */ sde_cfg->perf.min_prefill_lines = 21; } else if (IS_MSM8998_TARGET(hw_rev)) { /* update msm8998 target here */ sde_cfg->has_wb_ubwc = true; sde_cfg->perf.min_prefill_lines = 25; sde_cfg->vbif_qos_nlvl = 4; sde_cfg->ts_prefill_rev = 1; } else if (IS_SDM845_TARGET(hw_rev) || IS_SDM670_TARGET(hw_rev)) { /* update sdm845 target here */ } else if (IS_SDM845_TARGET(hw_rev)) { sde_cfg->has_wb_ubwc = true; sde_cfg->perf.min_prefill_lines = 24; sde_cfg->vbif_qos_nlvl = 8; sde_cfg->ts_prefill_rev = 2; sde_cfg->sui_misr_supported = true; sde_cfg->sui_block_xin_mask = 0x3F71; } else if (IS_SDM670_TARGET(hw_rev)) { sde_cfg->has_wb_ubwc = true; sde_cfg->perf.min_prefill_lines = 24; sde_cfg->vbif_qos_nlvl = 8; Loading @@ -3544,6 +3548,8 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0; sde_cfg->delay_prg_fetch_start = true; sde_cfg->sui_ns_allowed = true; sde_cfg->sui_misr_supported = true; sde_cfg->sui_block_xin_mask = 0x3F71; } else if (IS_SDMSHRIKE_TARGET(hw_rev)) { sde_cfg->has_wb_ubwc = true; sde_cfg->perf.min_prefill_lines = 24; Loading @@ -3569,6 +3575,10 @@ static int _sde_hardware_post_caps(struct sde_mdss_cfg *sde_cfg, if (!sde_cfg) return -EINVAL; if (IS_SM8150_TARGET(hw_rev)) sde_cfg->sui_supported_blendstage = sde_cfg->max_mixer_blendstages - SDE_STAGE_0; for (i = 0; i < sde_cfg->sspp_count; i++) { if (sde_cfg->sspp[i].sblk) { max_horz_deci = max(max_horz_deci, Loading
drivers/gpu/drm/msm/sde/sde_rm.c +1 −1 Original line number Diff line number Diff line Loading @@ -1211,7 +1211,7 @@ static u32 _sde_rm_poll_intr_status_for_cont_splash(struct sde_hw_intr *intr, } SDE_EVT32(status, irq_idx_pp_done, SDE_EVTLOG_ERROR); SDE_ERROR("polling timed out. status = 0x%x\n", status); SDE_DEBUG("polling timed out. status = 0x%x\n", status); return -ETIMEDOUT; } Loading
drivers/gpu/drm/msm/sde_io_util.c +24 −1 Original line number Diff line number Diff line /* Copyright (c) 2012-2015, 2017, The Linux Foundation. All rights reserved. /* Copyright (c) 2012-2015, 2017-2018 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and Loading Loading @@ -217,6 +217,7 @@ int msm_dss_enable_vreg(struct dss_vreg *in_vreg, int num_vreg, int enable) { int i = 0, rc = 0; bool need_sleep; int reg_mode; if (enable) { for (i = 0; i < num_vreg; i++) { Loading @@ -227,6 +228,17 @@ int msm_dss_enable_vreg(struct dss_vreg *in_vreg, int num_vreg, int enable) in_vreg[i].vreg_name, rc); goto vreg_set_opt_mode_fail; } reg_mode = regulator_get_mode(in_vreg[i].vreg); if (reg_mode == REGULATOR_MODE_FAST) { DEV_DBG("%pS->%s: %s operation not allowed\n", __builtin_return_address(0), __func__, in_vreg[i].vreg_name); /* * This regulator is controlled by Hw cannot be * controlled by Sw vote */ continue; } need_sleep = !regulator_is_enabled(in_vreg[i].vreg); if (in_vreg[i].pre_on_sleep && need_sleep) usleep_range(in_vreg[i].pre_on_sleep * 1000, Loading @@ -252,6 +264,17 @@ int msm_dss_enable_vreg(struct dss_vreg *in_vreg, int num_vreg, int enable) } } else { for (i = num_vreg-1; i >= 0; i--) { reg_mode = regulator_get_mode(in_vreg[i].vreg); if (reg_mode == REGULATOR_MODE_FAST) { DEV_DBG("%pS->%s: %s operation not allowed\n", __builtin_return_address(0), __func__, in_vreg[i].vreg_name); /* * This regulator is controlled by Hw cannot be * controlled by Sw vote */ continue; } if (in_vreg[i].pre_off_sleep) usleep_range(in_vreg[i].pre_off_sleep * 1000, in_vreg[i].pre_off_sleep * 1000); Loading