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Commit fe26adf4 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-for-v4.16-part2-fixes' of git://people.freedesktop.org/~airlied/linux 

Pull more drm updates from Dave Airlie:
 "Ben missed sending his nouveau tree, but he really didn't have much
  stuff in it:

   - GP108 acceleration support is enabled by "secure boot" support

   - some clockgating work on Kepler, and bunch of fixes

   - the bulk of the diff is regenerated firmware files, the change to
     them really isn't that large.

  Otherwise this contains regular Intel and AMDGPU fixes"

* tag 'drm-for-v4.16-part2-fixes' of git://people.freedesktop.org/~airlied/linux: (59 commits)
  drm/i915/bios: add DP max link rate to VBT child device struct
  drm/i915/cnp: Properly handle VBT ddc pin out of bounds.
  drm/i915/cnp: Ignore VBT request for know invalid DDC pin.
  drm/i915/cmdparser: Do not check past the cmd length.
  drm/i915/cmdparser: Check reg_table_count before derefencing.
  drm/i915/bxt, glk: Increase PCODE timeouts during CDCLK freq changing
  drm/i915/gvt: Use KVM r/w to access guest opregion
  drm/i915/gvt: Fix aperture read/write emulation when enable x-no-mmap=on
  drm/i915/gvt: only reset execlist state of one engine during VM engine reset
  drm/i915/gvt: refine intel_vgpu_submission_ops as per engine ops
  drm/amdgpu: re-enable CGCG on CZ and disable on ST
  drm/nouveau/clk: fix gcc-7 -Wint-in-bool-context warning
  drm/nouveau/mmu: Fix trailing semicolon
  drm/nouveau: Introduce NvPmEnableGating option
  drm/nouveau: Add support for SLCG for Kepler2
  drm/nouveau: Add support for BLCG on Kepler2
  drm/nouveau: Add support for BLCG on Kepler1
  drm/nouveau: Add support for basic clockgating on Kepler1
  drm/nouveau/kms/nv50: fix handling of gamma since atomic conversion
  drm/nouveau/kms/nv50: use INTERPOLATE_257_UNITY_RANGE LUT on newer chipsets
  ...
parents 9e95dae7 94fc27ac

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

+6 −2
Original line number Diff line number Diff line
@@ -179,8 +179,12 @@ static int amdgpu_gfx_kiq_acquire(struct amdgpu_device *adev, 


		amdgpu_gfx_bit_to_queue(adev, queue_bit, &mec, &pipe, &queue);



		/* Using pipes 2/3 from MEC 2 seems cause problems */

		if (mec == 1 && pipe > 1)

		/*

		 * 1. Using pipes 2/3 from MEC 2 seems cause problems.

		 * 2. It must use queue id 0, because CGPG_IDLE/SAVE/LOAD/RUN

		 * only can be issued on queue 0.

		 */

		if ((mec == 1 && pipe > 1) || queue != 0)

			continue;



		ring->me = mec + 1;

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

+12 −20
Original line number Diff line number Diff line
@@ -2262,12 +2262,12 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, 
{

	const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,

		AMDGPU_VM_PTE_COUNT(adev) * 8);

	uint64_t init_pde_value = 0, flags;

	unsigned ring_instance;

	struct amdgpu_ring *ring;

	struct drm_sched_rq *rq;

	unsigned long size;

	int r, i;

	u64 flags;

	uint64_t init_pde_value = 0;



	vm->va = RB_ROOT_CACHED;

	for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
@@ -2318,29 +2318,21 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, 
		flags |= (AMDGPU_GEM_CREATE_NO_CPU_ACCESS |

				AMDGPU_GEM_CREATE_SHADOW);



	r = amdgpu_bo_create(adev,

			     amdgpu_vm_bo_size(adev, adev->vm_manager.root_level),

			     align, true,

			     AMDGPU_GEM_DOMAIN_VRAM,

			     flags,

			     NULL, NULL, init_pde_value, &vm->root.base.bo);

	size = amdgpu_vm_bo_size(adev, adev->vm_manager.root_level);

	r = amdgpu_bo_create(adev, size, align, true, AMDGPU_GEM_DOMAIN_VRAM,

			     flags, NULL, NULL, init_pde_value,

			     &vm->root.base.bo);

	if (r)

		goto error_free_sched_entity;



	vm->root.base.vm = vm;

	list_add_tail(&vm->root.base.bo_list, &vm->root.base.bo->va);

	INIT_LIST_HEAD(&vm->root.base.vm_status);



	if (vm->use_cpu_for_update) {

		r = amdgpu_bo_reserve(vm->root.base.bo, false);

	r = amdgpu_bo_reserve(vm->root.base.bo, true);

	if (r)

		goto error_free_root;



		r = amdgpu_bo_kmap(vm->root.base.bo, NULL);

	vm->root.base.vm = vm;

	list_add_tail(&vm->root.base.bo_list, &vm->root.base.bo->va);

	list_add_tail(&vm->root.base.vm_status, &vm->evicted);

	amdgpu_bo_unreserve(vm->root.base.bo);

		if (r)

			goto error_free_root;

	}



	if (pasid) {

		unsigned long flags;

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

+4 −2
Original line number Diff line number Diff line
@@ -278,9 +278,9 @@ static bool vega10_ih_prescreen_iv(struct amdgpu_device *adev) 
	/* Track retry faults in per-VM fault FIFO. */

	spin_lock(&adev->vm_manager.pasid_lock);

	vm = idr_find(&adev->vm_manager.pasid_idr, pasid);

	spin_unlock(&adev->vm_manager.pasid_lock);

	if (WARN_ON_ONCE(!vm)) {

	if (!vm) {

		/* VM not found, process it normally */

		spin_unlock(&adev->vm_manager.pasid_lock);

		amdgpu_ih_clear_fault(adev, key);

		return true;

	}
@@ -288,9 +288,11 @@ static bool vega10_ih_prescreen_iv(struct amdgpu_device *adev) 
	r = kfifo_put(&vm->faults, key);

	if (!r) {

		/* FIFO is full. Ignore it until there is space */

		spin_unlock(&adev->vm_manager.pasid_lock);

		amdgpu_ih_clear_fault(adev, key);

		goto ignore_iv;

	}

	spin_unlock(&adev->vm_manager.pasid_lock);



	/* It's the first fault for this address, process it normally */

	return true;

drivers/gpu/drm/amd/amdgpu/vi.c

+0 −1
Original line number Diff line number Diff line
@@ -1049,7 +1049,6 @@ static int vi_common_early_init(void *handle) 
			AMD_CG_SUPPORT_GFX_CP_LS |

			AMD_CG_SUPPORT_GFX_CGTS |

			AMD_CG_SUPPORT_GFX_CGTS_LS |

			AMD_CG_SUPPORT_GFX_CGCG |

			AMD_CG_SUPPORT_GFX_CGLS |

			AMD_CG_SUPPORT_BIF_LS |

			AMD_CG_SUPPORT_HDP_MGCG |

drivers/gpu/drm/i915/gvt/cfg_space.c

+1 −14
Original line number Diff line number Diff line
@@ -119,16 +119,6 @@ static int map_aperture(struct intel_vgpu *vgpu, bool map) 
	if (map == vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked)

		return 0;



	if (map) {

		vgpu->gm.aperture_va = memremap(aperture_pa, aperture_sz,

						MEMREMAP_WC);

		if (!vgpu->gm.aperture_va)

			return -ENOMEM;

	} else {

		memunmap(vgpu->gm.aperture_va);

		vgpu->gm.aperture_va = NULL;

	}



	val = vgpu_cfg_space(vgpu)[PCI_BASE_ADDRESS_2];

	if (val & PCI_BASE_ADDRESS_MEM_TYPE_64)

		val = *(u64 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_2);
@@ -141,11 +131,8 @@ static int map_aperture(struct intel_vgpu *vgpu, bool map) 
						  aperture_pa >> PAGE_SHIFT,

						  aperture_sz >> PAGE_SHIFT,

						  map);

	if (ret) {

		memunmap(vgpu->gm.aperture_va);

		vgpu->gm.aperture_va = NULL;

	if (ret)

		return ret;

	}



	vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked = map;

	return 0;