Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 94fc27ac authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-fixes-2018-02-07' of... 

Merge tag 'drm-intel-next-fixes-2018-02-07' of git://anongit.freedesktop.org/drm/drm-intel into drm-next

Fix for pcode timeouts on BXT and GLK, cmdparser fixes and fixes
for new vbt version on CFL and CNL.

GVT contains vGPU reset enhancement, which refines vGPU reset flow
and the support of virtual aperture read/write when x-no-mmap=on
is set in KVM, which is required by a test case from Redhat and
also another fix for virtual OpRegion.

* tag 'drm-intel-next-fixes-2018-02-07' of git://anongit.freedesktop.org/drm/drm-intel:
  drm/i915/bios: add DP max link rate to VBT child device struct
  drm/i915/cnp: Properly handle VBT ddc pin out of bounds.
  drm/i915/cnp: Ignore VBT request for know invalid DDC pin.
  drm/i915/cmdparser: Do not check past the cmd length.
  drm/i915/cmdparser: Check reg_table_count before derefencing.
  drm/i915/bxt, glk: Increase PCODE timeouts during CDCLK freq changing
  drm/i915/gvt: Use KVM r/w to access guest opregion
  drm/i915/gvt: Fix aperture read/write emulation when enable x-no-mmap=on
  drm/i915/gvt: only reset execlist state of one engine during VM engine reset
  drm/i915/gvt: refine intel_vgpu_submission_ops as per engine ops
parents 2dd27794 6dd3104e

drivers/gpu/drm/i915/gvt/cfg_space.c

+1 −14
Original line number Diff line number Diff line
@@ -119,16 +119,6 @@ static int map_aperture(struct intel_vgpu *vgpu, bool map) 
	if (map == vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked)

		return 0;



	if (map) {

		vgpu->gm.aperture_va = memremap(aperture_pa, aperture_sz,

						MEMREMAP_WC);

		if (!vgpu->gm.aperture_va)

			return -ENOMEM;

	} else {

		memunmap(vgpu->gm.aperture_va);

		vgpu->gm.aperture_va = NULL;

	}



	val = vgpu_cfg_space(vgpu)[PCI_BASE_ADDRESS_2];

	if (val & PCI_BASE_ADDRESS_MEM_TYPE_64)

		val = *(u64 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_2);
@@ -141,11 +131,8 @@ static int map_aperture(struct intel_vgpu *vgpu, bool map) 
						  aperture_pa >> PAGE_SHIFT,

						  aperture_sz >> PAGE_SHIFT,

						  map);

	if (ret) {

		memunmap(vgpu->gm.aperture_va);

		vgpu->gm.aperture_va = NULL;

	if (ret)

		return ret;

	}



	vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked = map;

	return 0;

drivers/gpu/drm/i915/gvt/execlist.c

+11 −11
Original line number Diff line number Diff line
@@ -521,24 +521,23 @@ static void init_vgpu_execlist(struct intel_vgpu *vgpu, int ring_id) 


	ctx_status_ptr_reg = execlist_ring_mmio(vgpu->gvt, ring_id,

			_EL_OFFSET_STATUS_PTR);



	ctx_status_ptr.dw = vgpu_vreg(vgpu, ctx_status_ptr_reg);

	ctx_status_ptr.read_ptr = 0;

	ctx_status_ptr.write_ptr = 0x7;

	vgpu_vreg(vgpu, ctx_status_ptr_reg) = ctx_status_ptr.dw;

}



static void clean_execlist(struct intel_vgpu *vgpu)

static void clean_execlist(struct intel_vgpu *vgpu, unsigned long engine_mask)

{

	enum intel_engine_id i;

	unsigned int tmp;

	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;

	struct intel_engine_cs *engine;



	for_each_engine(engine, vgpu->gvt->dev_priv, i) {

	struct intel_vgpu_submission *s = &vgpu->submission;



		kfree(s->ring_scan_buffer[i]);

		s->ring_scan_buffer[i] = NULL;

		s->ring_scan_buffer_size[i] = 0;

	for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {

		kfree(s->ring_scan_buffer[engine->id]);

		s->ring_scan_buffer[engine->id] = NULL;

		s->ring_scan_buffer_size[engine->id] = 0;

	}

}
@@ -553,9 +552,10 @@ static void reset_execlist(struct intel_vgpu *vgpu, 
		init_vgpu_execlist(vgpu, engine->id);

}



static int init_execlist(struct intel_vgpu *vgpu)

static int init_execlist(struct intel_vgpu *vgpu,

			 unsigned long engine_mask)

{

	reset_execlist(vgpu, ALL_ENGINES);

	reset_execlist(vgpu, engine_mask);

	return 0;

}

drivers/gpu/drm/i915/gvt/gvt.h

+2 −4
Original line number Diff line number Diff line
@@ -82,7 +82,6 @@ struct intel_gvt_device_info { 
struct intel_vgpu_gm {

	u64 aperture_sz;

	u64 hidden_sz;

	void *aperture_va;

	struct drm_mm_node low_gm_node;

	struct drm_mm_node high_gm_node;

};
@@ -127,7 +126,6 @@ struct intel_vgpu_irq { 
struct intel_vgpu_opregion {

	bool mapped;

	void *va;

	void *va_gopregion;

	u32 gfn[INTEL_GVT_OPREGION_PAGES];

};
@@ -152,8 +150,8 @@ enum { 


struct intel_vgpu_submission_ops {

	const char *name;

	int (*init)(struct intel_vgpu *vgpu);

	void (*clean)(struct intel_vgpu *vgpu);

	int (*init)(struct intel_vgpu *vgpu, unsigned long engine_mask);

	void (*clean)(struct intel_vgpu *vgpu, unsigned long engine_mask);

	void (*reset)(struct intel_vgpu *vgpu, unsigned long engine_mask);

};

drivers/gpu/drm/i915/gvt/handlers.c

+2 −5
Original line number Diff line number Diff line
@@ -1494,7 +1494,6 @@ static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 
static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,

		void *p_data, unsigned int bytes)

{

	struct intel_vgpu_submission *s = &vgpu->submission;

	u32 data = *(u32 *)p_data;

	int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);

	bool enable_execlist;
@@ -1523,10 +1522,8 @@ static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 
		if (!enable_execlist)

			return 0;



		if (s->active)

			return 0;



		ret = intel_vgpu_select_submission_ops(vgpu,

			       ENGINE_MASK(ring_id),

			       INTEL_VGPU_EXECLIST_SUBMISSION);

		if (ret)

			return ret;

drivers/gpu/drm/i915/gvt/kvmgt.c

+34 −2
Original line number Diff line number Diff line
@@ -651,6 +651,39 @@ static int intel_vgpu_bar_rw(struct intel_vgpu *vgpu, int bar, uint64_t off, 
	return ret;

}



static inline bool intel_vgpu_in_aperture(struct intel_vgpu *vgpu, uint64_t off)

{

	return off >= vgpu_aperture_offset(vgpu) &&

	       off < vgpu_aperture_offset(vgpu) + vgpu_aperture_sz(vgpu);

}



static int intel_vgpu_aperture_rw(struct intel_vgpu *vgpu, uint64_t off,

		void *buf, unsigned long count, bool is_write)

{

	void *aperture_va;



	if (!intel_vgpu_in_aperture(vgpu, off) ||

	    !intel_vgpu_in_aperture(vgpu, off + count)) {

		gvt_vgpu_err("Invalid aperture offset %llu\n", off);

		return -EINVAL;

	}



	aperture_va = io_mapping_map_wc(&vgpu->gvt->dev_priv->ggtt.iomap,

					ALIGN_DOWN(off, PAGE_SIZE),

					count + offset_in_page(off));

	if (!aperture_va)

		return -EIO;



	if (is_write)

		memcpy(aperture_va + offset_in_page(off), buf, count);

	else

		memcpy(buf, aperture_va + offset_in_page(off), count);



	io_mapping_unmap(aperture_va);



	return 0;

}



static ssize_t intel_vgpu_rw(struct mdev_device *mdev, char *buf,

			size_t count, loff_t *ppos, bool is_write)

{
@@ -679,8 +712,7 @@ static ssize_t intel_vgpu_rw(struct mdev_device *mdev, char *buf, 
					buf, count, is_write);

		break;

	case VFIO_PCI_BAR2_REGION_INDEX:

		ret = intel_vgpu_bar_rw(vgpu, PCI_BASE_ADDRESS_2, pos,

					buf, count, is_write);

		ret = intel_vgpu_aperture_rw(vgpu, pos, buf, count, is_write);

		break;

	case VFIO_PCI_BAR1_REGION_INDEX:

	case VFIO_PCI_BAR3_REGION_INDEX: