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Commit fd0d351d authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'tty-4.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty 

Pull tty/serial driver updates from Greg KH:
 "Here is the big tty and serial driver update for 4.4-rc1.

  Lots of serial driver updates and a few small tty core changes.  Full
  details in the shortlog.

  All of these have been in linux-next for a while"

* tag 'tty-4.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty: (148 commits)
  tty: Use unbound workqueue for all input workers
  tty: Abstract tty buffer work
  tty: Prevent tty teardown during tty_write_message()
  tty: core: Use correct spinlock flavor in tiocspgrp()
  tty: Combine SIGTTOU/SIGTTIN handling
  serial: amba-pl011: fix incorrect integer size in pl011_fifo_to_tty()
  ttyFDC: Fix build problems due to use of module_{init,exit}
  tty: remove unneeded return statement
  serial: 8250_mid: add support for DMA engine handling from UART MMIO
  dmaengine: hsu: remove platform data
  dmaengine: hsu: introduce stubs for the exported functions
  dmaengine: hsu: make the UART driver in control of selecting this driver
  serial: fix mctrl helper functions
  serial: 8250_pci: Intel MID UART support to its own driver
  serial: fsl_lpuart: add earlycon support
  tty: disable unbind for old 74xx based serial/mpsc console port
  serial: pl011: Spelling s/clocks-names/clock-names/
  n_tty: Remove reader wakeups for TTY_BREAK/TTY_PARITY chars
  tty: synclink, fix indentation
  serial: at91, fix rs485 properties
  ...
parents 3d6f4780 e052c6d1

Documentation/devicetree/bindings/serial/ingenic,uart.txt

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* Ingenic SoC UART



Required properties:

- compatible : "ingenic,jz4740-uart" or "ingenic,jz4780-uart"

- compatible : "ingenic,jz4740-uart", "ingenic,jz4760-uart",

	"ingenic,jz4775-uart" or "ingenic,jz4780-uart"

- reg : offset and length of the register set for the device.

- interrupts : should contain uart interrupt.

- clocks : phandles to the module & baud clocks.

Documentation/devicetree/bindings/serial/pl011.txt

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@@ -19,7 +19,7 @@ Optional properties: 
	   must correspond to the PCLK clocking the internal logic

	   of the block. Just listing one clock (the first one) is

	   deprecated.

- clocks-names:

- clock-names:

	   When present, the first clock listed must be named

	   "uartclk" and the second clock listed must be named

	   "apb_pclk"

Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt

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@@ -26,6 +26,12 @@ Required properties: 
Optional properties:

- dmas: Should contain dma specifiers for transmit and receive channels

- dma-names: Should contain "tx" for transmit and "rx" for receive channels

- qcom,tx-crci: Identificator <u32> for Client Rate Control Interface to be

           used with TX DMA channel. Required when using DMA for transmission

           with UARTDM v1.3 and bellow.

- qcom,rx-crci: Identificator <u32> for Client Rate Control Interface to be

           used with RX DMA channel. Required when using DMA for reception

           with UARTDM v1.3 and bellow.



Note: Aliases may be defined to ensure the correct ordering of the UARTs.

The alias serialN will result in the UART being assigned port N.  If any

Documentation/devicetree/bindings/serial/renesas,sci-serial.txt

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@@ -23,6 +23,8 @@ Required properties: 
    - "renesas,scifa-r8a7794" for R8A7794 (R-Car E2) SCIFA compatible UART.

    - "renesas,scifb-r8a7794" for R8A7794 (R-Car E2) SCIFB compatible UART.

    - "renesas,hscif-r8a7794" for R8A7794 (R-Car E2) HSCIF compatible UART.

    - "renesas,scif-r8a7795" for R8A7795 (R-Car H3) SCIF compatible UART.

    - "renesas,hscif-r8a7795" for R8A7795 (R-Car H3) HSCIF compatible UART.

    - "renesas,scifa-sh73a0" for SH73A0 (SH-Mobile AG5) SCIFA compatible UART.

    - "renesas,scifb-sh73a0" for SH73A0 (SH-Mobile AG5) SCIFB compatible UART.

    - "renesas,scif" for generic SCIF compatible UART.

Documentation/devicetree/bindings/serial/snps-dw-apb-uart.txt

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@@ -15,6 +15,9 @@ The supplying peripheral clock can also be handled, needing a second property 
	Required elements: "baudclk", "apb_pclk"



Optional properties:

- snps,uart-16550-compatible : reflects the value of UART_16550_COMPATIBLE

  configuration parameter. Define this if your UART does not implement the busy

  functionality.

- resets : phandle to the parent reset controller.

- reg-shift : quantity to shift the register offsets by.  If this property is

  not present then the register offsets are not shifted.