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Commit f85c6edf authored by Michael Turquette's avatar Michael Turquette
Browse files

Merge tag 'tegra-clk-3.20' of git://nv-tegra.nvidia.com/user/pdeschrijver/linux into clk-next 

Tegra clock fixes for 3.20
parents 54eea32f b270491e

Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt

+6 −4
Original line number Diff line number Diff line 
NVIDIA Tegra124 Clock And Reset Controller

NVIDIA Tegra124 and Tegra132 Clock And Reset Controller



This binding uses the common clock binding:

Documentation/devicetree/bindings/clock/clock-bindings.txt
@@ -7,14 +7,16 @@ The CAR (Clock And Reset) Controller on Tegra is the HW module responsible 
for muxing and gating Tegra's clocks, and setting their rates.



Required properties :

- compatible : Should be "nvidia,tegra124-car"

- compatible : Should be "nvidia,tegra124-car" or "nvidia,tegra132-car"

- reg : Should contain CAR registers location and length

- clocks : Should contain phandle and clock specifiers for two clocks:

  the 32 KHz "32k_in", and the board-specific oscillator "osc".

- #clock-cells : Should be 1.

  In clock consumers, this cell represents the clock ID exposed by the

  CAR. The assignments may be found in header file

  <dt-bindings/clock/tegra124-car.h>.

  CAR. The assignments may be found in the header files

  <dt-bindings/clock/tegra124-car-common.h> (which covers IDs common

  to Tegra124 and Tegra132) and <dt-bindings/clock/tegra124-car.h>

  (for Tegra124-specific clocks).

- #reset-cells : Should be 1.

  In clock consumers, this cell represents the bit number in the CAR's

  array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.

arch/arm/mach-tegra/tegra.c

+0 −2
Original line number Diff line number Diff line
@@ -91,8 +91,6 @@ static void __init tegra_dt_init(void) 
	struct soc_device *soc_dev;

	struct device *parent = NULL;



	tegra_clocks_apply_init_table();



	soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);

	if (!soc_dev_attr)

		goto out;

drivers/clk/tegra/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -15,3 +15,4 @@ obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o 
obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += clk-tegra30.o

obj-$(CONFIG_ARCH_TEGRA_114_SOC)	+= clk-tegra114.o

obj-$(CONFIG_ARCH_TEGRA_124_SOC)	+= clk-tegra124.o

obj-$(CONFIG_ARCH_TEGRA_132_SOC)	+= clk-tegra124.o

drivers/clk/tegra/clk-id.h

+0 −2
Original line number Diff line number Diff line
@@ -64,10 +64,8 @@ enum clk_id { 
	tegra_clk_disp2,

	tegra_clk_dp2,

	tegra_clk_dpaux,

	tegra_clk_dsia,

	tegra_clk_dsialp,

	tegra_clk_dsia_mux,

	tegra_clk_dsib,

	tegra_clk_dsiblp,

	tegra_clk_dsib_mux,

	tegra_clk_dtv,

drivers/clk/tegra/clk-pll.c

+11 −7
Original line number Diff line number Diff line
@@ -816,7 +816,9 @@ const struct clk_ops tegra_clk_plle_ops = { 
	.enable = clk_plle_enable,

};



#if defined(CONFIG_ARCH_TEGRA_114_SOC) || defined(CONFIG_ARCH_TEGRA_124_SOC)

#if defined(CONFIG_ARCH_TEGRA_114_SOC) || \

	defined(CONFIG_ARCH_TEGRA_124_SOC) || \

	defined(CONFIG_ARCH_TEGRA_132_SOC)



static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,

			   unsigned long parent_rate)
@@ -1505,7 +1507,9 @@ struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, 
	return clk;

}



#if defined(CONFIG_ARCH_TEGRA_114_SOC) || defined(CONFIG_ARCH_TEGRA_124_SOC)

#if defined(CONFIG_ARCH_TEGRA_114_SOC) || \

	defined(CONFIG_ARCH_TEGRA_124_SOC) || \

	defined(CONFIG_ARCH_TEGRA_132_SOC)

static const struct clk_ops tegra_clk_pllxc_ops = {

	.is_enabled = clk_pll_is_enabled,

	.enable = clk_pll_iddq_enable,
@@ -1565,7 +1569,7 @@ struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, 
	parent = __clk_lookup(parent_name);

	if (!parent) {

		WARN(1, "parent clk %s of %s must be registered first\n",

			name, parent_name);

			parent_name, name);

		return ERR_PTR(-EINVAL);

	}
@@ -1665,7 +1669,7 @@ struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name, 
	parent = __clk_lookup(parent_name);

	if (!parent) {

		WARN(1, "parent clk %s of %s must be registered first\n",

			name, parent_name);

			parent_name, name);

		return ERR_PTR(-EINVAL);

	}
@@ -1706,7 +1710,7 @@ struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name, 
	parent = __clk_lookup(parent_name);

	if (!parent) {

		WARN(1, "parent clk %s of %s must be registered first\n",

			name, parent_name);

			parent_name, name);

		return ERR_PTR(-EINVAL);

	}
@@ -1802,7 +1806,7 @@ struct clk *tegra_clk_register_plle_tegra114(const char *name, 
}

#endif



#ifdef CONFIG_ARCH_TEGRA_124_SOC

#if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC)

static const struct clk_ops tegra_clk_pllss_ops = {

	.is_enabled = clk_pll_is_enabled,

	.enable = clk_pll_iddq_enable,
@@ -1830,7 +1834,7 @@ struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name, 
	parent = __clk_lookup(parent_name);

	if (!parent) {

		WARN(1, "parent clk %s of %s must be registered first\n",

			name, parent_name);

			parent_name, name);

		return ERR_PTR(-EINVAL);

	}