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Commit 54eea32f authored by Michael Turquette's avatar Michael Turquette
Browse files

Merge branch 'clk-next' into v3.19-rc7

parents e36f014e b530e7d2

Documentation/clk.txt

+2 −0
Original line number Diff line number Diff line
@@ -73,6 +73,8 @@ the operations defined in clk.h: 
						unsigned long *parent_rate);

		long		(*determine_rate)(struct clk_hw *hw,

						unsigned long rate,

						unsigned long min_rate,

						unsigned long max_rate,

						unsigned long *best_parent_rate,

						struct clk_hw **best_parent_clk);

		int		(*set_parent)(struct clk_hw *hw, u8 index);

Documentation/devicetree/bindings/clock/exynos7-clock.txt

+15 −0
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@@ -34,6 +34,8 @@ Required Properties for Clock Controller: 
	- "samsung,exynos7-clock-peris"

	- "samsung,exynos7-clock-fsys0"

	- "samsung,exynos7-clock-fsys1"

	- "samsung,exynos7-clock-mscl"

	- "samsung,exynos7-clock-aud"



 - reg: physical base address of the controller and the length of

	memory mapped region.
@@ -53,6 +55,7 @@ Input clocks for top0 clock controller: 
	- dout_sclk_bus1_pll

	- dout_sclk_cc_pll

	- dout_sclk_mfc_pll

	- dout_sclk_aud_pll



Input clocks for top1 clock controller:

	- fin_pll
@@ -76,6 +79,14 @@ Input clocks for peric1 clock controller: 
	- sclk_uart1

	- sclk_uart2

	- sclk_uart3

	- sclk_spi0

	- sclk_spi1

	- sclk_spi2

	- sclk_spi3

	- sclk_spi4

	- sclk_i2s1

	- sclk_pcm1

	- sclk_spdif



Input clocks for peris clock controller:

	- fin_pll
@@ -91,3 +102,7 @@ Input clocks for fsys1 clock controller: 
	- dout_aclk_fsys1_200

	- dout_sclk_mmc0

	- dout_sclk_mmc1



Input clocks for aud clock controller:

	- fin_pll

	- fout_aud_pll

Documentation/devicetree/bindings/clock/qcom,lcc.txt

0 → 100644
+21 −0
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Qualcomm LPASS Clock & Reset Controller Binding

------------------------------------------------



Required properties :

- compatible : shall contain only one of the following:



			"qcom,lcc-msm8960"

			"qcom,lcc-apq8064"

			"qcom,lcc-ipq8064"



- reg : shall contain base register location and length

- #clock-cells : shall contain 1

- #reset-cells : shall contain 1



Example:

	clock-controller@28000000 {

		compatible = "qcom,lcc-ipq8064";

		reg = <0x28000000 0x1000>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};

Documentation/devicetree/bindings/clock/qoriq-clock.txt

+3 −2
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* Clock Block on Freescale CoreNet Platforms

* Clock Block on Freescale QorIQ Platforms



Freescale CoreNet chips take primary clocking input from the external

Freescale qoriq chips take primary clocking input from the external

SYSCLK signal. The SYSCLK input (frequency) is multiplied using

multiple phase locked loops (PLL) to create a variety of frequencies

which can then be passed to a variety of internal logic, including
@@ -29,6 +29,7 @@ Required properties: 
	* "fsl,t4240-clockgen"

	* "fsl,b4420-clockgen"

	* "fsl,b4860-clockgen"

	* "fsl,ls1021a-clockgen"

	Chassis clock strings include:

	* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks

	* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks

Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt

+1 −0
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@@ -11,6 +11,7 @@ Required Properties: 


  - compatible: Must be one of the following

    - "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks

    - "renesas,r8a73a4-mstp-clocks" for R8A73A4 (R-Mobile APE6) MSTP gate clocks

    - "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks

    - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks

    - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks