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Commit f5e1648c authored by Priit Laes's avatar Priit Laes Committed by Maxime Ripard
Browse files

ARM: sun4i: A10: Add display and TCON clocks 



Enable the display and TCON clocks that are needed to drive the display
engine, tcon and TV encoders.

Signed-off-by: default avatarPriit Laes <plaes@plaes.org>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent eee25ab1

arch/arm/boot/dts/sun4i-a10.dtsi

+85 −11
Original line number Diff line number Diff line
@@ -65,9 +65,8 @@ 
			compatible = "allwinner,simple-framebuffer",

				     "simple-framebuffer";

			allwinner,pipeline = "de_be0-lcd0-hdmi";

			clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,

				 <&ahb_gates 43>, <&ahb_gates 44>,

				 <&dram_gates 26>;

			clocks = <&ahb_gates 36>, <&ahb_gates 43>, <&ahb_gates 44>,

				 <&de_be0_clk>, <&tcon0_ch0_clk>, <&dram_gates 26>;

			status = "disabled";

		};
@@ -75,9 +74,9 @@ 
			compatible = "allwinner,simple-framebuffer",

				     "simple-framebuffer";

			allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";

			clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,

				 <&ahb_gates 43>, <&ahb_gates 44>,

				 <&ahb_gates 46>,

			clocks = <&ahb_gates 36>, <&ahb_gates 43>,

				 <&ahb_gates 44>, <&ahb_gates 46>,

				 <&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch0_clk>,

				 <&dram_gates 25>, <&dram_gates 26>;

			status = "disabled";

		};
@@ -86,8 +85,8 @@ 
			compatible = "allwinner,simple-framebuffer",

				     "simple-framebuffer";

			allwinner,pipeline = "de_fe0-de_be0-lcd0";

			clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,

				 <&ahb_gates 44>, <&ahb_gates 46>,

			clocks = <&ahb_gates 36>, <&ahb_gates 44>, <&ahb_gates 46>,

				 <&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch0_clk>,

				 <&dram_gates 25>, <&dram_gates 26>;

			status = "disabled";

		};
@@ -96,9 +95,9 @@ 
			compatible = "allwinner,simple-framebuffer",

				     "simple-framebuffer";

			allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";

			clocks = <&pll3>, <&pll5 1>, <&ahb_gates 34>,

				 <&ahb_gates 36>, <&ahb_gates 44>,

				 <&ahb_gates 46>,

			clocks = <&ahb_gates 34>, <&ahb_gates 36>,

				 <&ahb_gates 44>, <&ahb_gates 46>,

				 <&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch0_clk>,

				 <&dram_gates 5>, <&dram_gates 25>, <&dram_gates 26>;

			status = "disabled";

		};
@@ -577,6 +576,81 @@ 
					     "dram_de_mp", "dram_ace";

		};



		de_be0_clk: clk@01c20104 {

			#clock-cells = <0>;

			#reset-cells = <0>;

			compatible = "allwinner,sun4i-a10-display-clk";

			reg = <0x01c20104 0x4>;

			clocks = <&pll3>, <&pll7>, <&pll5 1>;

			clock-output-names = "de-be0";

		};



		de_be1_clk: clk@01c20108 {

			#clock-cells = <0>;

			#reset-cells = <0>;

			compatible = "allwinner,sun4i-a10-display-clk";

			reg = <0x01c20108 0x4>;

			clocks = <&pll3>, <&pll7>, <&pll5 1>;

			clock-output-names = "de-be1";

		};



		de_fe0_clk: clk@01c2010c {

			#clock-cells = <0>;

			#reset-cells = <0>;

			compatible = "allwinner,sun4i-a10-display-clk";

			reg = <0x01c2010c 0x4>;

			clocks = <&pll3>, <&pll7>, <&pll5 1>;

			clock-output-names = "de-fe0";

		};



		de_fe1_clk: clk@01c20110 {

			#clock-cells = <0>;

			#reset-cells = <0>;

			compatible = "allwinner,sun4i-a10-display-clk";

			reg = <0x01c20110 0x4>;

			clocks = <&pll3>, <&pll7>, <&pll5 1>;

			clock-output-names = "de-fe1";

		};





		tcon0_ch0_clk: clk@01c20118 {

			#clock-cells = <0>;

			#reset-cells = <1>;

			compatible = "allwinner,sun4i-a10-tcon-ch0-clk";

			reg = <0x01c20118 0x4>;

			clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;

			clock-output-names = "tcon0-ch0-sclk";



		};



		tcon1_ch0_clk: clk@01c2011c {

			#clock-cells = <0>;

			#reset-cells = <1>;

			compatible = "allwinner,sun4i-a10-tcon-ch1-clk";

			reg = <0x01c2011c 0x4>;

			clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;

			clock-output-names = "tcon1-ch0-sclk";



		};



		tcon0_ch1_clk: clk@01c2012c {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-a10-tcon-ch0-clk";

			reg = <0x01c2012c 0x4>;

			clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;

			clock-output-names = "tcon0-ch1-sclk";



		};



		tcon1_ch1_clk: clk@01c20130 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-a10-tcon-ch1-clk";

			reg = <0x01c20130 0x4>;

			clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;

			clock-output-names = "tcon1-ch1-sclk";



		};



		ve_clk: clk@01c2013c {

			#clock-cells = <0>;

			#reset-cells = <0>;