Loading arch/arm/boot/dts/dra7.dtsi +1 −1 Original line number Diff line number Diff line Loading @@ -742,7 +742,7 @@ }; wdt2: wdt@4ae14000 { compatible = "ti,omap4-wdt"; compatible = "ti,omap3-wdt"; reg = <0x4ae14000 0x80>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "wd_timer2"; Loading arch/arm/boot/dts/dra7xx-clocks.dtsi +3 −3 Original line number Diff line number Diff line Loading @@ -1042,7 +1042,7 @@ #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&sys_clkin2>; reg = <0x01a4>; reg = <0x0164>; }; mlb_clk: mlb_clk { Loading Loading @@ -1084,14 +1084,14 @@ #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&sys_clkin2>; reg = <0x01d0>; reg = <0x0168>; }; video2_dpll_clk_mux: video2_dpll_clk_mux { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&sys_clkin2>; reg = <0x01d4>; reg = <0x016c>; }; wkupaon_iclk_mux: wkupaon_iclk_mux { Loading arch/arm/mach-omap2/clock.h +0 −2 Original line number Diff line number Diff line Loading @@ -270,8 +270,6 @@ extern const struct clksel_rate div31_1to31_rates[]; extern void __iomem *clk_memmaps[]; extern int am33xx_clk_init(void); extern int omap2_clkops_enable_clkdm(struct clk_hw *hw); extern void omap2_clkops_disable_clkdm(struct clk_hw *hw); Loading Loading
arch/arm/boot/dts/dra7.dtsi +1 −1 Original line number Diff line number Diff line Loading @@ -742,7 +742,7 @@ }; wdt2: wdt@4ae14000 { compatible = "ti,omap4-wdt"; compatible = "ti,omap3-wdt"; reg = <0x4ae14000 0x80>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "wd_timer2"; Loading
arch/arm/boot/dts/dra7xx-clocks.dtsi +3 −3 Original line number Diff line number Diff line Loading @@ -1042,7 +1042,7 @@ #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&sys_clkin2>; reg = <0x01a4>; reg = <0x0164>; }; mlb_clk: mlb_clk { Loading Loading @@ -1084,14 +1084,14 @@ #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&sys_clkin2>; reg = <0x01d0>; reg = <0x0168>; }; video2_dpll_clk_mux: video2_dpll_clk_mux { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&sys_clkin2>; reg = <0x01d4>; reg = <0x016c>; }; wkupaon_iclk_mux: wkupaon_iclk_mux { Loading
arch/arm/mach-omap2/clock.h +0 −2 Original line number Diff line number Diff line Loading @@ -270,8 +270,6 @@ extern const struct clksel_rate div31_1to31_rates[]; extern void __iomem *clk_memmaps[]; extern int am33xx_clk_init(void); extern int omap2_clkops_enable_clkdm(struct clk_hw *hw); extern void omap2_clkops_disable_clkdm(struct clk_hw *hw); Loading