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Commit e671538d authored by Tomi Valkeinen's avatar Tomi Valkeinen Committed by Tony Lindgren
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ARM: dts: dra7: fix DSS PLL clock mux registers 



The clock nodes for DSS VIDEO1/2 and HDMI have wrong register addresses.
This patch fixes the addresses so that they point to
CM_CLKSEL_VIDEO1_PLL_SYS, CM_CLKSEL_VIDEO2_PLL_SYS and
CM_CLKSEL_HDMI_PLL_SYS.

Reported-by: default avatarSomnath Mukherjee <somnath@ti.com>
Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: default avatarTero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent be668835

arch/arm/boot/dts/dra7xx-clocks.dtsi

+3 −3
Original line number Diff line number Diff line
@@ -1042,7 +1042,7 @@ 
		#clock-cells = <0>;

		compatible = "ti,mux-clock";

		clocks = <&sys_clkin1>, <&sys_clkin2>;

		reg = <0x01a4>;

		reg = <0x0164>;

	};



	mlb_clk: mlb_clk {
@@ -1084,14 +1084,14 @@ 
		#clock-cells = <0>;

		compatible = "ti,mux-clock";

		clocks = <&sys_clkin1>, <&sys_clkin2>;

		reg = <0x01d0>;

		reg = <0x0168>;

	};



	video2_dpll_clk_mux: video2_dpll_clk_mux {

		#clock-cells = <0>;

		compatible = "ti,mux-clock";

		clocks = <&sys_clkin1>, <&sys_clkin2>;

		reg = <0x01d4>;

		reg = <0x016c>;

	};



	wkupaon_iclk_mux: wkupaon_iclk_mux {