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Commit f2fe1b64 authored by Chen-Yu Tsai's avatar Chen-Yu Tsai Committed by Maxime Ripard
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clk: sunxi-ng: a83t: Fix audio PLL divider offset 



The divider of the audio PLL has an offset of 1.
Fix this in the driver.

Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent faea8b0e

drivers/clk/sunxi-ng/ccu-sun8i-a83t.c

+1 −1
Original line number Diff line number Diff line
@@ -80,7 +80,7 @@ static struct ccu_nm pll_audio_clk = { 
	.enable		= BIT(31),

	.lock		= BIT(2),

	.n		= _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),

	.m		= _SUNXI_CCU_DIV_OFFSET(0, 6, 0),

	.m		= _SUNXI_CCU_DIV(0, 6),

	.common		= {

		.reg		= SUN8I_A83T_PLL_AUDIO_REG,

		.lock_reg	= CCU_SUN8I_A83T_LOCK_REG,