Commit faea8b0e authored May 22, 2017 by Chen-Yu Tsai Committed by Maxime Ripard Jun 07, 2017

clk: sunxi-ng: a83t: Fix PLL lock status register offset



The offset for the PLL lock status register was incorrectly set to
0x208, which actually points to an unused register. The correct
register offset is 0x20c.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

parent 05359be1

drivers/clk/sunxi-ng/ccu-sun8i-a83t.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -28,7 +28,7 @@

		#include "ccu-sun8i-a83t.h"

		#define CCU_SUN8I_A83T_LOCK_REG 0x208
		#define CCU_SUN8I_A83T_LOCK_REG 0x20c

		/*
		* The CPU PLLs are actually NP clocks, with P being /1 or /4. However