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Commit f215a57d authored by Eric Yang's avatar Eric Yang Committed by Alex Deucher
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drm/amd/display: update infoframe after dig fe is turned on 



Before dig fe is enabled, infoframe can't be programmed. So in
suspend resume case our infoframe programmming was not going through.

This change changes the sequence so that infoframe is programmed
after.

Signed-off-by: default avatarEric Yang <Eric.Yang2@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 28d41754

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

+13 −10
Original line number Diff line number Diff line
@@ -684,15 +684,22 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx) 
	struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;

	struct dc_link *link = pipe_ctx->stream->sink->link;



	/* 1. update AVI info frame (HDMI, DP)

	 * we always need to update info frame

	*/



	uint32_t active_total_with_borders;

	uint32_t early_control = 0;

	struct timing_generator *tg = pipe_ctx->stream_res.tg;



	/* TODOFPGA may change to hwss.update_info_frame */

	/* For MST, there are multiply stream go to only one link.

	 * connect DIG back_end to front_end while enable_stream and

	 * disconnect them during disable_stream

	 * BY this, it is logic clean to separate stream and link */

	link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,

						    pipe_ctx->stream_res.stream_enc->id, true);



	/* update AVI info frame (HDMI, DP)*/

	/* TODO: FPGA may change to hwss.update_info_frame */

	dce110_update_info_frame(pipe_ctx);



	/* enable early control to avoid corruption on DP monitor*/

	active_total_with_borders =

			timing->h_addressable
@@ -713,12 +720,8 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx) 
			pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);

	}



	/* For MST, there are multiply stream go to only one link.

	 * connect DIG back_end to front_end while enable_stream and

	 * disconnect them during disable_stream

	 * BY this, it is logic clean to separate stream and link */

	link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,

						    pipe_ctx->stream_res.stream_enc->id, true);







}