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Commit efd814b7 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
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drm/i915: Polish the chv cmnlane resrt macros 



Replace the semi-funky cmnlane assert/deassert macros with something a
bit more conventional. Also protect the macro arguments properly (also
for  PHY_POWERGOOD()).

Reviewed-by: default avatarRafael Barbalho <rafael.barbalho@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 3dd7b974

drivers/gpu/drm/i915/i915_reg.h

+2 −5
Original line number Diff line number Diff line
@@ -1697,12 +1697,9 @@ enum punit_power_well { 
#define DPIO_PHY_STATUS			(VLV_DISPLAY_BASE + 0x6240)

#define   DPLL_PORTD_READY_MASK		(0xf)

#define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100)

#define   PHY_COM_LANE_RESET_DEASSERT(phy, val) \

				((phy == DPIO_PHY0) ? (val | 1) : (val | 2))

#define   PHY_COM_LANE_RESET_ASSERT(phy, val) \

				((phy == DPIO_PHY0) ? (val & ~1) : (val & ~2))

#define   PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy))

#define DISPLAY_PHY_STATUS (VLV_DISPLAY_BASE + 0x60104)

#define   PHY_POWERGOOD(phy)	((phy == DPIO_PHY0) ? (1<<31) : (1<<30))

#define   PHY_POWERGOOD(phy)	(((phy) == DPIO_PHY0) ? (1<<31) : (1<<30))



/*

 * The i830 generation, in LVDS mode, defines P1 as the bit number set within

drivers/gpu/drm/i915/intel_pm.c

+4 −4
Original line number Diff line number Diff line
@@ -6359,8 +6359,8 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 
	if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))

		DRM_ERROR("Display PHY %d is not power up\n", phy);



	I915_WRITE(DISPLAY_PHY_CONTROL,

		   PHY_COM_LANE_RESET_DEASSERT(phy, I915_READ(DISPLAY_PHY_CONTROL)));

	I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) |

		   PHY_COM_LANE_RESET_DEASSERT(phy));

}



static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
@@ -6380,8 +6380,8 @@ static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 
		assert_pll_disabled(dev_priv, PIPE_C);

	}



	I915_WRITE(DISPLAY_PHY_CONTROL,

		   PHY_COM_LANE_RESET_ASSERT(phy, I915_READ(DISPLAY_PHY_CONTROL)));

	I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) &

		   ~PHY_COM_LANE_RESET_DEASSERT(phy));



	vlv_set_power_well(dev_priv, power_well, false);

}