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Commit 3dd7b974 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
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drm/i915: Hack to tie both common lanes together on chv 



It looks like frobbing the cmnreset line on pne PHY disturbs the other
PHY on chv. The result is a black screen. On HDMI it's just a flash of
black, but DP usually falls over and can't get back up.

As a workaround set up the power domains so that both common lane
wells power up and down together. I also tried leaving the cmnreset
deasserted even the if the power well goes down but that didn't seem
acceptable to the PHY.

Reviewed-by: default avatarRafael Barbalho <rafael.barbalho@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 3c2777fd

drivers/gpu/drm/i915/intel_pm.c

+12 −2
Original line number Diff line number Diff line
@@ -6877,13 +6877,23 @@ static struct i915_power_well chv_power_wells[] = { 
#endif

	{

		.name = "dpio-common-bc",

		.domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,

		/*

		 * XXX: cmnreset for one PHY seems to disturb the other.

		 * As a workaround keep both powered on at the same

		 * time for now.

		 */

		.domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS,

		.data = PUNIT_POWER_WELL_DPIO_CMN_BC,

		.ops = &chv_dpio_cmn_power_well_ops,

	},

	{

		.name = "dpio-common-d",

		.domains = CHV_DPIO_CMN_D_POWER_DOMAINS,

		/*

		 * XXX: cmnreset for one PHY seems to disturb the other.

		 * As a workaround keep both powered on at the same

		 * time for now.

		 */

		.domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS,

		.data = PUNIT_POWER_WELL_DPIO_CMN_D,

		.ops = &chv_dpio_cmn_power_well_ops,

	},