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Commit ec75a716 authored by Ingo Molnar's avatar Ingo Molnar
Browse files

perf events, x86: Work around the Nehalem AAJ80 erratum 



On Nehalem CPUs the retired branch-misses event can be completely bogus,
when there are no branch-misses occuring. When there are a lot of branch
misses then the count is pretty accurate. Still, this leaves us with an
event that over-counts a lot.

Detect this erratum and work it around by using BR_MISP_EXEC.ANY events.
These will also count speculated branches but still it's a lot more
precise in practice than the architectural event.

Acked-by: default avatarPeter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Link: http://lkml.kernel.org/n/tip-yyfg0bxo9jsqxd6a0ovfny27@git.kernel.org


Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent 18a073a3

arch/x86/kernel/cpu/perf_event_intel.c

+14 −2
Original line number Diff line number Diff line
@@ -25,7 +25,7 @@ struct intel_percore { 
/*

 * Intel PerfMon, used on Core and later.

 */

static const u64 intel_perfmon_event_map[] =

static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =

{

  [PERF_COUNT_HW_CPU_CYCLES]		= 0x003c,

  [PERF_COUNT_HW_INSTRUCTIONS]		= 0x00c0,
@@ -1412,6 +1412,18 @@ static __init int intel_pmu_init(void) 
		x86_pmu.percore_constraints = intel_nehalem_percore_constraints;

		x86_pmu.enable_all = intel_pmu_nhm_enable_all;

		x86_pmu.extra_regs = intel_nehalem_extra_regs;



		if (ebx & 0x40) {

			/*

			 * Erratum AAJ80 detected, we work it around by using

			 * the BR_MISP_EXEC.ANY event. This will over-count

			 * branch-misses, but it's still much better than the

			 * architectural event which is often completely bogus:

			 */

			intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;



			pr_cont("erratum AAJ80 worked around, ");

		}

		pr_cont("Nehalem events, ");

		break;