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Commit e87f327e authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc 

Pull sparc fixes from David Miller:

 1) Fix TLB context wrap races, from Pavel Tatashin.

 2) Cure some gcc-7 build issues.

 3) Handle invalid setup_hugepagesz command line values properly, from
    Liam R Howlett.

 4) Copy TSB using the correct address shift for the huge TSB, from Mike
    Kravetz.

* git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc:
  sparc64: delete old wrap code
  sparc64: new context wrap
  sparc64: add per-cpu mm of secondary contexts
  sparc64: redefine first version
  sparc64: combine activate_mm and switch_mm
  sparc64: reset mm cpumask after wrap
  sparc/mm/hugepages: Fix setup_hugepagesz for invalid values.
  sparc: Machine description indices can vary
  sparc64: mm: fix copy_tsb to correctly copy huge page TSBs
  arch/sparc: support NR_CPUS = 4096
  sparc64: Add __multi3 for gcc 7.x and later.
  sparc64: Fix build warnings with gcc 7.
  arch/sparc: increase CONFIG_NODES_SHIFT on SPARC64 to 5
parents abb2ea7d b3aefc2f

arch/sparc/Kconfig

+8 −4
Original line number Diff line number Diff line
@@ -192,9 +192,9 @@ config NR_CPUS 
	int "Maximum number of CPUs"

	depends on SMP

	range 2 32 if SPARC32

	range 2 1024 if SPARC64

	range 2 4096 if SPARC64

	default 32 if SPARC32

	default 64 if SPARC64

	default 4096 if SPARC64



source kernel/Kconfig.hz
@@ -295,9 +295,13 @@ config NUMA 
	depends on SPARC64 && SMP



config NODES_SHIFT

	int

	default "4"

	int "Maximum NUMA Nodes (as a power of 2)"

	range 4 5 if SPARC64

	default "5"

	depends on NEED_MULTIPLE_NODES

	help

	  Specify the maximum number of NUMA Nodes available on the target

	  system.  Increases memory reserved to accommodate various tables.



# Some NUMA nodes have memory ranges that span

# other nodes.  Even though a pfn is valid and

arch/sparc/include/asm/mmu_64.h

+1 −1
Original line number Diff line number Diff line
@@ -52,7 +52,7 @@ 
#define CTX_NR_MASK		TAG_CONTEXT_BITS

#define CTX_HW_MASK		(CTX_NR_MASK | CTX_PGSZ_MASK)



#define CTX_FIRST_VERSION	((_AC(1,UL) << CTX_VERSION_SHIFT) + _AC(1,UL))

#define CTX_FIRST_VERSION	BIT(CTX_VERSION_SHIFT)

#define CTX_VALID(__ctx)	\

	 (!(((__ctx.sparc64_ctx_val) ^ tlb_context_cache) & CTX_VERSION_MASK))

#define CTX_HWBITS(__ctx)	((__ctx.sparc64_ctx_val) & CTX_HW_MASK)

arch/sparc/include/asm/mmu_context_64.h

+4 −28
Original line number Diff line number Diff line
@@ -19,13 +19,8 @@ extern spinlock_t ctx_alloc_lock; 
extern unsigned long tlb_context_cache;

extern unsigned long mmu_context_bmap[];



DECLARE_PER_CPU(struct mm_struct *, per_cpu_secondary_mm);

void get_new_mmu_context(struct mm_struct *mm);

#ifdef CONFIG_SMP

void smp_new_mmu_context_version(void);

#else

#define smp_new_mmu_context_version() do { } while (0)

#endif



int init_new_context(struct task_struct *tsk, struct mm_struct *mm);

void destroy_context(struct mm_struct *mm);
@@ -76,8 +71,9 @@ void __flush_tlb_mm(unsigned long, unsigned long); 
static inline void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, struct task_struct *tsk)

{

	unsigned long ctx_valid, flags;

	int cpu;

	int cpu = smp_processor_id();



	per_cpu(per_cpu_secondary_mm, cpu) = mm;

	if (unlikely(mm == &init_mm))

		return;
@@ -123,7 +119,6 @@ static inline void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, str 
	 * for the first time, we must flush that context out of the

	 * local TLB.

	 */

	cpu = smp_processor_id();

	if (!ctx_valid || !cpumask_test_cpu(cpu, mm_cpumask(mm))) {

		cpumask_set_cpu(cpu, mm_cpumask(mm));

		__flush_tlb_mm(CTX_HWBITS(mm->context),
@@ -133,26 +128,7 @@ static inline void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, str 
}



#define deactivate_mm(tsk,mm)	do { } while (0)



/* Activate a new MM instance for the current task. */

static inline void activate_mm(struct mm_struct *active_mm, struct mm_struct *mm)

{

	unsigned long flags;

	int cpu;



	spin_lock_irqsave(&mm->context.lock, flags);

	if (!CTX_VALID(mm->context))

		get_new_mmu_context(mm);

	cpu = smp_processor_id();

	if (!cpumask_test_cpu(cpu, mm_cpumask(mm)))

		cpumask_set_cpu(cpu, mm_cpumask(mm));



	load_secondary_context(mm);

	__flush_tlb_mm(CTX_HWBITS(mm->context), SECONDARY_CONTEXT);

	tsb_context_switch(mm);

	spin_unlock_irqrestore(&mm->context.lock, flags);

}



#define activate_mm(active_mm, mm) switch_mm(active_mm, mm, NULL)

#endif /* !(__ASSEMBLY__) */



#endif /* !(__SPARC64_MMU_CONTEXT_H) */

arch/sparc/include/asm/pil.h

+0 −1
Original line number Diff line number Diff line
@@ -20,7 +20,6 @@ 
#define PIL_SMP_CALL_FUNC	1

#define PIL_SMP_RECEIVE_SIGNAL	2

#define PIL_SMP_CAPTURE		3

#define PIL_SMP_CTX_NEW_VERSION	4

#define PIL_DEVICE_IRQ		5

#define PIL_SMP_CALL_FUNC_SNGL	6

#define PIL_DEFERRED_PCR_WORK	7

arch/sparc/include/asm/vio.h

+1 −0
Original line number Diff line number Diff line
@@ -327,6 +327,7 @@ struct vio_dev { 
	int			compat_len;



	u64			dev_no;

	u64			id;



	unsigned long		channel_id;