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Commit e8740644 authored by Srinivas Kandagatla's avatar Srinivas Kandagatla Committed by Ulf Hansson
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mmc: mmci: add edge support to data and command out in variant data. 



This patch adds edge support for data and command out to variant structure
giving more flexibility to the driver to support more SOCs which have
different clock register layout.

Without this patch other new SOCs like Qcom will have to add more code to
special case them

Signed-off-by: default avatarSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: default avatarLinus Walleij <linus.walleij@linaro.org>
[Ulf Hansson] Resolved conflict
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent e1412d85

drivers/mmc/host/mmci.c

+5 −1
Original line number Original line Diff line number Diff line
@@ -53,6 +53,7 @@ static unsigned int fmax = 515633; 
 * @clkreg: default value for MCICLOCK register

 * @clkreg: default value for MCICLOCK register

 * @clkreg_enable: enable value for MMCICLOCK register

 * @clkreg_enable: enable value for MMCICLOCK register

 * @clkreg_8bit_bus_enable: enable value for 8 bit bus

 * @clkreg_8bit_bus_enable: enable value for 8 bit bus

 * @clkreg_neg_edge_enable: enable value for inverted data/cmd output

 * @datalength_bits: number of bits in the MMCIDATALENGTH register

 * @datalength_bits: number of bits in the MMCIDATALENGTH register

 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY

 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY

 *	      is asserted (likewise for RX)

 *	      is asserted (likewise for RX)
@@ -74,6 +75,7 @@ struct variant_data { 
	unsigned int		clkreg;

	unsigned int		clkreg;

	unsigned int		clkreg_enable;

	unsigned int		clkreg_enable;

	unsigned int		clkreg_8bit_bus_enable;

	unsigned int		clkreg_8bit_bus_enable;

	unsigned int		clkreg_neg_edge_enable;

	unsigned int		datalength_bits;

	unsigned int		datalength_bits;

	unsigned int		fifosize;

	unsigned int		fifosize;

	unsigned int		fifohalfsize;

	unsigned int		fifohalfsize;
@@ -143,6 +145,7 @@ static struct variant_data variant_ux500 = { 
	.clkreg			= MCI_CLK_ENABLE,

	.clkreg			= MCI_CLK_ENABLE,

	.clkreg_enable		= MCI_ST_UX500_HWFCEN,

	.clkreg_enable		= MCI_ST_UX500_HWFCEN,

	.clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,

	.clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,

	.clkreg_neg_edge_enable	= MCI_ST_UX500_NEG_EDGE,

	.datalength_bits	= 24,

	.datalength_bits	= 24,

	.sdio			= true,

	.sdio			= true,

	.st_clkdiv		= true,

	.st_clkdiv		= true,
@@ -159,6 +162,7 @@ static struct variant_data variant_ux500v2 = { 
	.clkreg			= MCI_CLK_ENABLE,

	.clkreg			= MCI_CLK_ENABLE,

	.clkreg_enable		= MCI_ST_UX500_HWFCEN,

	.clkreg_enable		= MCI_ST_UX500_HWFCEN,

	.clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,

	.clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,

	.clkreg_neg_edge_enable	= MCI_ST_UX500_NEG_EDGE,

	.datactrl_mask_ddrmode	= MCI_ST_DPSM_DDRMODE,

	.datactrl_mask_ddrmode	= MCI_ST_DPSM_DDRMODE,

	.datalength_bits	= 24,

	.datalength_bits	= 24,

	.sdio			= true,

	.sdio			= true,
@@ -314,7 +318,7 @@ static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 




	if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||

	if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||

	    host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)

	    host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)

		clk |= MCI_ST_UX500_NEG_EDGE;

		clk |= variant->clkreg_neg_edge_enable;





	mmci_write_clkreg(host, clk);

	mmci_write_clkreg(host, clk);

}

}