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Commit e1412d85 authored by Srinivas Kandagatla's avatar Srinivas Kandagatla Committed by Ulf Hansson
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mmc: mmci: add 8bit bus support in variant data 



This patch adds 8bit bus enable to variant structure giving more flexibility
to the driver to support more SOCs which have different clock register layout.

Without this patch other new SOCs like Qcom will have to add more code
to special case them.

Signed-off-by: default avatarSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: default avatarLinus Walleij <linus.walleij@linaro.org>
[Ulf Hansson] Resolved conflict
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent e17dca2b

drivers/mmc/host/mmci.c

+6 −1
Original line number Diff line number Diff line
@@ -52,6 +52,7 @@ static unsigned int fmax = 515633; 
 * struct variant_data - MMCI variant-specific quirks

 * @clkreg: default value for MCICLOCK register

 * @clkreg_enable: enable value for MMCICLOCK register

 * @clkreg_8bit_bus_enable: enable value for 8 bit bus

 * @datalength_bits: number of bits in the MMCIDATALENGTH register

 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY

 *	      is asserted (likewise for RX)
@@ -72,6 +73,7 @@ static unsigned int fmax = 515633; 
struct variant_data {

	unsigned int		clkreg;

	unsigned int		clkreg_enable;

	unsigned int		clkreg_8bit_bus_enable;

	unsigned int		datalength_bits;

	unsigned int		fifosize;

	unsigned int		fifohalfsize;
@@ -113,6 +115,7 @@ static struct variant_data variant_u300 = { 
	.fifosize		= 16 * 4,

	.fifohalfsize		= 8 * 4,

	.clkreg_enable		= MCI_ST_U300_HWFCEN,

	.clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,

	.datalength_bits	= 16,

	.sdio			= true,

	.pwrreg_powerup		= MCI_PWR_ON,
@@ -139,6 +142,7 @@ static struct variant_data variant_ux500 = { 
	.fifohalfsize		= 8 * 4,

	.clkreg			= MCI_CLK_ENABLE,

	.clkreg_enable		= MCI_ST_UX500_HWFCEN,

	.clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,

	.datalength_bits	= 24,

	.sdio			= true,

	.st_clkdiv		= true,
@@ -154,6 +158,7 @@ static struct variant_data variant_ux500v2 = { 
	.fifohalfsize		= 8 * 4,

	.clkreg			= MCI_CLK_ENABLE,

	.clkreg_enable		= MCI_ST_UX500_HWFCEN,

	.clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,

	.datactrl_mask_ddrmode	= MCI_ST_DPSM_DDRMODE,

	.datalength_bits	= 24,

	.sdio			= true,
@@ -305,7 +310,7 @@ static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 
	if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)

		clk |= MCI_4BIT_BUS;

	if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)

		clk |= MCI_ST_8BIT_BUS;

		clk |= variant->clkreg_8bit_bus_enable;



	if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||

	    host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)