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Commit dce8efa0 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'hisi-arm64-dt-for-4.17' of git://github.com/hisilicon/linux-hisi into next/dt 

Pull "ARM64: DT: Hisilicon SoC DT updates for 4.17" from Wei Xu:

- Add XGE CPLD control support for hip07 SoC
- Disable the SMMU on hip06 and hip07 SoCs becuase of
  the hardware limitation
- Enable HS200 mode for the MMC controller on hi6220 hikey board
- Remove "cooling-{min|max}-level" this kind unused properties
  for hi6220 SoC
- Add watchdog node for hi6220 SoC
- Remove "CPU_NAP" idle state on hikey960 board since it is
  not stable and useless with the updated firmware

* tag 'hisi-arm64-dt-for-4.17' of git://github.com/hisilicon/linux-hisi:
  arm64: dts: Hi3660: Remove 'CPU_NAP' idle state
  arm64: dts: hi6220: enable watchdog
  ARM64: dts: hi6220: Remove "cooling-{min|max}-level" for CPU nodes
  arm64: dts: hikey: Enable HS200 mode on eMMC
  arm64: dts: hisi: Disable hisilicon smmu node on hip06/hip07
  arm64: dts: hisi: add hns-dsaf cpld control for the hip07 SoC
parents 4bb4acea 928c4a5c

arch/arm64/boot/dts/hisilicon/hi3660.dtsi

+4 −28
Original line number Diff line number Diff line
@@ -100,11 +100,7 @@ 
			reg = <0x0 0x100>;

			enable-method = "psci";

			next-level-cache = <&A73_L2>;

			cpu-idle-states = <

					&CPU_NAP

					&CPU_SLEEP

					&CLUSTER_SLEEP_1

			>;

			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>;

			capacity-dmips-mhz = <1024>;

		};
@@ -114,11 +110,7 @@ 
			reg = <0x0 0x101>;

			enable-method = "psci";

			next-level-cache = <&A73_L2>;

			cpu-idle-states = <

					&CPU_NAP

					&CPU_SLEEP

					&CLUSTER_SLEEP_1

			>;

			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>;

			capacity-dmips-mhz = <1024>;

		};
@@ -128,11 +120,7 @@ 
			reg = <0x0 0x102>;

			enable-method = "psci";

			next-level-cache = <&A73_L2>;

			cpu-idle-states = <

					&CPU_NAP

					&CPU_SLEEP

					&CLUSTER_SLEEP_1

			>;

			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>;

			capacity-dmips-mhz = <1024>;

		};
@@ -142,25 +130,13 @@ 
			reg = <0x0 0x103>;

			enable-method = "psci";

			next-level-cache = <&A73_L2>;

			cpu-idle-states = <

					&CPU_NAP

					&CPU_SLEEP

					&CLUSTER_SLEEP_1

			>;

			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>;

			capacity-dmips-mhz = <1024>;

		};



		idle-states {

			entry-method = "psci";



			CPU_NAP: cpu-nap {

				compatible = "arm,idle-state";

				arm,psci-suspend-param = <0x0000001>;

				entry-latency-us = <7>;

				exit-latency-us = <2>;

				min-residency-us = <15>;

			};



			CPU_SLEEP: cpu-sleep {

				compatible = "arm,idle-state";

				local-timer-stop;

arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts

+2 −0
Original line number Diff line number Diff line
@@ -299,7 +299,9 @@ 
		/* GPIO blocks 16 thru 19 do not appear to be routed to pins */



		dwmmc_0: dwmmc0@f723d000 {

			max-frequency = <150000000>;

			cap-mmc-highspeed;

			mmc-hs200-1_8v;

			non-removable;

			bus-width = <0x8>;

			vmmc-supply = <&ldo19>;

arch/arm64/boot/dts/hisilicon/hi6220.dtsi

+8 −2
Original line number Diff line number Diff line
@@ -88,8 +88,6 @@ 
			next-level-cache = <&CLUSTER0_L2>;

			clocks = <&stub_clock 0>;

			operating-points-v2 = <&cpu_opp_table>;

			cooling-min-level = <4>;

			cooling-max-level = <0>;

			#cooling-cells = <2>; /* min followed by max */

			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;

			dynamic-power-coefficient = <311>;
@@ -817,6 +815,14 @@ 
			pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>;

		};



		watchdog0: watchdog@f8005000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			reg = <0x0 0xf8005000 0x0 0x1000>;

			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&ao_ctrl HI6220_WDT0_PCLK>;

			clock-names = "apb_pclk";

		};



		tsensor: tsensor@0,f7030700 {

			compatible = "hisilicon,tsensor";

			reg = <0x0 0xf7030700 0x0 0x1000>;

arch/arm64/boot/dts/hisilicon/hip06.dtsi

+56 −0
Original line number Diff line number Diff line
@@ -291,6 +291,13 @@ 
			#interrupt-cells = <2>;

			num-pins = <128>;

		};



		mbigen_pcie0: intc_pcie0 {

			msi-parent = <&its_dsa 0x40085>;

			interrupt-controller;

			#interrupt-cells = <2>;

			num-pins = <10>;

		};

	};



	mbigen_dsa@c0080000 {
@@ -312,6 +319,31 @@ 
		};

	};



	/**

	 *  HiSilicon erratum 161010801: This describes the limitation

	 *  of HiSilicon platforms hip06/hip07 to support the SMMUv3

	 *  mappings for PCIe MSI transactions.

	 *  PCIe controller on these platforms has to differentiate the

	 *  MSI payload against other DMA payload and has to modify the

	 *  MSI payload. This makes it difficult for these platforms to

	 *  have a SMMU translation for MSI. In order to workaround this,

	 *  ARM SMMUv3 driver requires a quirk to treat the MSI regions

	 *  separately. Such a quirk is currently missing for DT based

	 *  systems. Hence please make sure that the smmu pcie node on

	 *  hip06 is disabled as this will break the PCIe functionality

	 *  when iommu-map entry is used along with the PCIe node.

	 *  Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html

	 */

	smmu0: smmu_pcie {

		compatible = "arm,smmu-v3";

		reg = <0x0 0xa0040000 0x0 0x20000>;

		#iommu-cells = <1>;

		dma-coherent;

		smmu-cb-memtype = <0x0 0x1>;

		hisilicon,broken-prefetch-cmd;

		status = "disabled";

	};



	soc {

		compatible = "simple-bus";

		#address-cells = <2>;
@@ -676,6 +708,30 @@ 
				     <637 1>,<638 1>,<639 1>;

			status = "disabled";

		};



		pcie0: pcie@a0090000 {

			compatible = "hisilicon,hip06-pcie-ecam";

			reg = <0 0xb0000000 0 0x2000000>,

			      <0 0xa0090000 0 0x10000>;

			bus-range = <0  31>;

			msi-map = <0x0000 &its_dsa 0x0000 0x2000>;

			msi-map-mask = <0xffff>;

			#address-cells = <3>;

			#size-cells = <2>;

			device_type = "pci";

			dma-coherent;

			ranges = <0x02000000 0 0xb2000000 0x0 0xb2000000 0

				 0x5ff0000 0x01000000 0 0 0 0xb7ff0000

				 0 0x10000>;

			#interrupt-cells = <1>;

			interrupt-map-mask = <0xf800 0 0 7>;

			interrupt-map = <0x0 0 0 1 &mbigen_pcie0 650 4

					0x0 0 0 2 &mbigen_pcie0 650 4

					0x0 0 0 3 &mbigen_pcie0 650 4

					0x0 0 0 4 &mbigen_pcie0 650 4>;

			status = "disabled";

		};



	};



};

arch/arm64/boot/dts/hisilicon/hip07.dtsi

+33 −0
Original line number Diff line number Diff line
@@ -1083,6 +1083,31 @@ 
		};

	};



	/**

	 *  HiSilicon erratum 161010801: This describes the limitation

	 *  of HiSilicon platforms hip06/hip07 to support the SMMUv3

	 *  mappings for PCIe MSI transactions.

	 *  PCIe controller on these platforms has to differentiate the

	 *  MSI payload against other DMA payload and has to modify the

	 *  MSI payload. This makes it difficult for these platforms to

	 *  have a SMMU translation for MSI. In order to workaround this,

	 *  ARM SMMUv3 driver requires a quirk to treat the MSI regions

	 *  separately. Such a quirk is currently missing for DT based

	 *  systems. Hence please make sure that the smmu pcie node on

	 *  hip07 is disabled as this will break the PCIe functionality

	 *  when iommu-map entry is used along with the PCIe node.

	 *  Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html

	 */

	smmu0: smmu_pcie {

		compatible = "arm,smmu-v3";

		reg = <0x0 0xa0040000 0x0 0x20000>;

		#iommu-cells = <1>;

		dma-coherent;

		smmu-cb-memtype = <0x0 0x1>;

		hisilicon,broken-prefetch-cmd;

		status = "disabled";

	};



	soc {

		compatible = "simple-bus";

		#address-cells = <2>;
@@ -1127,6 +1152,12 @@ 
			reg = <0x0 0xc0000000 0x0 0x10000>;

		};



		dsa_cpld: dsa_cpld@78000010 {

			compatible = "syscon";

			reg = <0x0 0x78000010 0x0 0x100>;

			reg-io-width = <2>;

		};



		pcie_subctl: pcie_subctl@a0000000 {

			compatible = "hisilicon,pcie-sas-subctrl", "syscon";

			reg = <0x0 0xa0000000 0x0 0x10000>;
@@ -1258,6 +1289,7 @@ 
			port@0 {

				reg = <0>;

				serdes-syscon = <&serdes_ctrl>;

				cpld-syscon = <&dsa_cpld 0x0>;

				port-rst-offset = <0>;

				port-mode-offset = <0>;

				mc-mac-mask = [ff f0 00 00 00 00];
@@ -1267,6 +1299,7 @@ 
			port@1 {

				reg = <1>;

				serdes-syscon= <&serdes_ctrl>;

				cpld-syscon = <&dsa_cpld 0x4>;

				port-rst-offset = <1>;

				port-mode-offset = <1>;

				mc-mac-mask = [ff f0 00 00 00 00];