Loading include/dt-bindings/clock/qcom,gcc-lagoon.h +4 −0 Original line number Diff line number Diff line Loading @@ -150,6 +150,8 @@ #define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 140 #define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 141 #define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 142 #define GCC_RX5_PCIE_CLKREF_CLK 143 #define GCC_GPU_GPLL0_MAIN_DIV_CLK_SRC 144 /* GCC resets */ #define GCC_QUSB2PHY_PRIM_BCR 0 Loading @@ -162,5 +164,7 @@ #define GCC_PCIE_0_PHY_BCR 7 #define GCC_QUPV3_WRAPPER_0_BCR 8 #define GCC_QUPV3_WRAPPER_1_BCR 9 #define GCC_USB3_PHY_PRIM_BCR 10 #define GCC_USB3_DP_PHY_PRIM_BCR 11 #endif Loading
include/dt-bindings/clock/qcom,gcc-lagoon.h +4 −0 Original line number Diff line number Diff line Loading @@ -150,6 +150,8 @@ #define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 140 #define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 141 #define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 142 #define GCC_RX5_PCIE_CLKREF_CLK 143 #define GCC_GPU_GPLL0_MAIN_DIV_CLK_SRC 144 /* GCC resets */ #define GCC_QUSB2PHY_PRIM_BCR 0 Loading @@ -162,5 +164,7 @@ #define GCC_PCIE_0_PHY_BCR 7 #define GCC_QUPV3_WRAPPER_0_BCR 8 #define GCC_QUPV3_WRAPPER_1_BCR 9 #define GCC_USB3_PHY_PRIM_BCR 10 #define GCC_USB3_DP_PHY_PRIM_BCR 11 #endif