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Commit f7249804 authored by Diptanshu Jamgade's avatar Diptanshu Jamgade
Browse files

dt-bindings: clock: qcom: Add support for clocks and BCRs in GCC for Lagoon 



Add support for gcc_rx5_pcie_clkref_clk, gcc_gpu_pll0_main_div_clk_src,
gcc_usb3_phy_prim_bcr and gcc_usb3_dp_phy_prim_bcr for Lagoon.

Change-Id: I4a55f475d363cc220dea8e7e51c4e0c8e3bacc4e
Signed-off-by: default avatarDiptanshu Jamgade <djamgade@codeaurora.org>
parent dbb7cabe

include/dt-bindings/clock/qcom,gcc-lagoon.h

+4 −0
Original line number Original line Diff line number Diff line
@@ -150,6 +150,8 @@ 
#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK	140

#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK	140

#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK	141

#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK	141

#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK		142

#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK		142

#define GCC_RX5_PCIE_CLKREF_CLK			143

#define GCC_GPU_GPLL0_MAIN_DIV_CLK_SRC		144





/* GCC resets */

/* GCC resets */

#define GCC_QUSB2PHY_PRIM_BCR			0

#define GCC_QUSB2PHY_PRIM_BCR			0
@@ -162,5 +164,7 @@ 
#define GCC_PCIE_0_PHY_BCR			7

#define GCC_PCIE_0_PHY_BCR			7

#define GCC_QUPV3_WRAPPER_0_BCR			8

#define GCC_QUPV3_WRAPPER_0_BCR			8

#define GCC_QUPV3_WRAPPER_1_BCR			9

#define GCC_QUPV3_WRAPPER_1_BCR			9

#define GCC_USB3_PHY_PRIM_BCR			10

#define GCC_USB3_DP_PHY_PRIM_BCR		11





#endif
 
#endif