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Commit d89f2071 authored by Rodrigo Vivi's avatar Rodrigo Vivi Committed by Daniel Vetter
Browse files

drm/i915: HSW FBC WaFbcDisableDpfcClockGating 



Display register 46500h bit 23 must be set to 1b for the entire time that
Frame Buffer Compression is enabled.

v2: Ville suggested to enable it back when disabling fbc to avoid wasting
    power.

v3: RMW to preserve other bits (by Ville)
v4: Fix from Ville: sed &/| at RMW
v5: Too far on sed.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@gmail.com>
[danvet: Insert missing space that checkpatch spotted.]
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 28554164

drivers/gpu/drm/i915/i915_reg.h

+3 −0
Original line number Diff line number Diff line
@@ -987,6 +987,9 @@ 
					     _HSW_PIPE_SLICE_CHICKEN_1_A, + \

					     _HSW_PIPE_SLICE_CHICKEN_1_B)



#define HSW_CLKGATE_DISABLE_PART_1	0x46500

#define   HSW_DPFC_GATING_DISABLE	(1<<23)



/*

 * GPIO regs

 */

drivers/gpu/drm/i915/intel_pm.c

+10 −0
Original line number Diff line number Diff line
@@ -248,6 +248,12 @@ static void ironlake_disable_fbc(struct drm_device *dev) 
				   I915_READ(ILK_DSPCLK_GATE_D) &

				   ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE);



		if (IS_HASWELL(dev))

			/* WaFbcDisableDpfcClockGating */

			I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,

				   I915_READ(HSW_CLKGATE_DISABLE_PART_1) &

				   ~HSW_DPFC_GATING_DISABLE);



		DRM_DEBUG_KMS("disabled FBC\n");

	}

}
@@ -285,6 +291,10 @@ static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval) 
		/* WaFbcAsynchFlipDisableFbcQueue */

		I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),

			   HSW_BYPASS_FBC_QUEUE);

		/* WaFbcDisableDpfcClockGating */

		I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,

			   I915_READ(HSW_CLKGATE_DISABLE_PART_1) |

			   HSW_DPFC_GATING_DISABLE);

	}



	I915_WRITE(SNB_DPFC_CTL_SA,