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Commit 28554164 authored by Rodrigo Vivi's avatar Rodrigo Vivi Committed by Daniel Vetter
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drm/i915: HSW FBC WaFbcAsynchFlipDisableFbcQueue 



Display register 420B0h bit 22 must be set to 1b for the entire time that
Frame Buffer Compression is enabled.

Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 891348b2

drivers/gpu/drm/i915/i915_reg.h

+7 −0
Original line number Diff line number Diff line
@@ -980,6 +980,13 @@ 
#define IVB_FBC_RT_BASE			0x7020





#define _HSW_PIPE_SLICE_CHICKEN_1_A	0x420B0

#define _HSW_PIPE_SLICE_CHICKEN_1_B	0x420B4

#define   HSW_BYPASS_FBC_QUEUE		(1<<22)

#define HSW_PIPE_SLICE_CHICKEN_1(pipe) _PIPE(pipe, + \

					     _HSW_PIPE_SLICE_CHICKEN_1_A, + \

					     _HSW_PIPE_SLICE_CHICKEN_1_B)



/*

 * GPIO regs

 */

drivers/gpu/drm/i915/intel_pm.c

+4 −0
Original line number Diff line number Diff line
@@ -281,6 +281,10 @@ static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval) 
		I915_WRITE(ILK_DSPCLK_GATE_D,

			   I915_READ(ILK_DSPCLK_GATE_D) |

			   ILK_DPFCUNIT_CLOCK_GATE_DISABLE);

	} else {

		/* WaFbcAsynchFlipDisableFbcQueue */

		I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),

			   HSW_BYPASS_FBC_QUEUE);

	}



	I915_WRITE(SNB_DPFC_CTL_SA,