Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 891348b2 authored by Rodrigo Vivi's avatar Rodrigo Vivi Committed by Daniel Vetter
Browse files

drm/i915: Enable FBC at Haswell. 



This patch introduce Frame Buffer Compression (FBC) support for HSW.
FBC is tied to primary plane A in HSW.

v2: Ville pointed out docs say FBC must be disabled before disabling
    the plane on HSW.
v3: Really enabling it by default at HSW.

Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@gmail.com>
Tested-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent b74ea102

drivers/gpu/drm/i915/i915_drv.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -319,6 +319,7 @@ static const struct intel_device_info intel_haswell_m_info = { 
	.is_mobile = 1,

	.is_mobile = 1,

	.has_ddi = 1,

	.has_ddi = 1,

	.has_fpga_dbg = 1,

	.has_fpga_dbg = 1,

	.has_fbc = 1,

};

};





static const struct pci_device_id pciidlist[] = {		/* aka */

static const struct pci_device_id pciidlist[] = {		/* aka */

drivers/gpu/drm/i915/intel_display.c

+3 −2
Original line number Original line Diff line number Diff line
@@ -3518,11 +3518,12 @@ static void haswell_crtc_disable(struct drm_crtc *crtc) 
	drm_vblank_off(dev, pipe);

	drm_vblank_off(dev, pipe);

	intel_crtc_update_cursor(crtc, false);

	intel_crtc_update_cursor(crtc, false);





	intel_disable_plane(dev_priv, plane, pipe);

	/* FBC must be disabled before disabling the plane on HSW. */



	if (dev_priv->cfb_plane == plane)

	if (dev_priv->cfb_plane == plane)

		intel_disable_fbc(dev);

		intel_disable_fbc(dev);





	intel_disable_plane(dev_priv, plane, pipe);



	if (intel_crtc->config.has_pch_encoder)

	if (intel_crtc->config.has_pch_encoder)

		intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);

		intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);

	intel_disable_pipe(dev_priv, pipe);

	intel_disable_pipe(dev_priv, pipe);

drivers/gpu/drm/i915/intel_pm.c

+12 −9
Original line number Original line Diff line number Diff line
@@ -274,12 +274,14 @@ static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval) 
		   IVB_DPFC_CTL_FENCE_EN |

		   IVB_DPFC_CTL_FENCE_EN |

		   intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);

		   intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);





	if (IS_IVYBRIDGE(dev)) {

		/* WaFbcAsynchFlipDisableFbcQueue */

		/* WaFbcAsynchFlipDisableFbcQueue */

		I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);

		I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);

		/* WaFbcDisableDpfcClockGating */

		/* WaFbcDisableDpfcClockGating */

		I915_WRITE(ILK_DSPCLK_GATE_D,

		I915_WRITE(ILK_DSPCLK_GATE_D,

			   I915_READ(ILK_DSPCLK_GATE_D) |

			   I915_READ(ILK_DSPCLK_GATE_D) |

			   ILK_DPFCUNIT_CLOCK_GATE_DISABLE);

			   ILK_DPFCUNIT_CLOCK_GATE_DISABLE);

	}





	I915_WRITE(SNB_DPFC_CTL_SA,

	I915_WRITE(SNB_DPFC_CTL_SA,

		   SNB_CPU_FENCE_ENABLE | obj->fence_reg);

		   SNB_CPU_FENCE_ENABLE | obj->fence_reg);
@@ -476,7 +478,7 @@ void intel_update_fbc(struct drm_device *dev) 
	if (enable_fbc < 0) {

	if (enable_fbc < 0) {

		DRM_DEBUG_KMS("fbc set to per-chip default\n");

		DRM_DEBUG_KMS("fbc set to per-chip default\n");

		enable_fbc = 1;

		enable_fbc = 1;

		if (INTEL_INFO(dev)->gen <= 7)

		if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))

			enable_fbc = 0;

			enable_fbc = 0;

	}

	}

	if (!enable_fbc) {

	if (!enable_fbc) {
@@ -497,7 +499,8 @@ void intel_update_fbc(struct drm_device *dev) 
		dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;

		dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;

		goto out_disable;

		goto out_disable;

	}

	}

	if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {

	if ((IS_I915GM(dev) || IS_I945GM(dev) || IS_HASWELL(dev)) &&

	    intel_crtc->plane != 0) {

		DRM_DEBUG_KMS("plane not 0, disabling compression\n");

		DRM_DEBUG_KMS("plane not 0, disabling compression\n");

		dev_priv->no_fbc_reason = FBC_BAD_PLANE;

		dev_priv->no_fbc_reason = FBC_BAD_PLANE;

		goto out_disable;

		goto out_disable;
@@ -4544,7 +4547,7 @@ void intel_init_pm(struct drm_device *dev) 
	if (I915_HAS_FBC(dev)) {

	if (I915_HAS_FBC(dev)) {

		if (HAS_PCH_SPLIT(dev)) {

		if (HAS_PCH_SPLIT(dev)) {

			dev_priv->display.fbc_enabled = ironlake_fbc_enabled;

			dev_priv->display.fbc_enabled = ironlake_fbc_enabled;

			if (IS_IVYBRIDGE(dev))

			if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))

				dev_priv->display.enable_fbc =

				dev_priv->display.enable_fbc =

					gen7_enable_fbc;

					gen7_enable_fbc;

			else

			else