Loading Documentation/sound/hd-audio/notes.rst +2 −0 Original line number Original line Diff line number Diff line Loading @@ -494,6 +494,8 @@ add_hp_mic (bool) hp_mic_detect (bool) hp_mic_detect (bool) enable/disable the hp/mic shared input for a single built-in mic enable/disable the hp/mic shared input for a single built-in mic case; default true case; default true vmaster (bool) enable/disable the virtual Master control; default true mixer_nid (int) mixer_nid (int) specifies the widget NID of the analog-loopback mixer specifies the widget NID of the analog-loopback mixer Loading include/sound/hda_register.h +25 −5 Original line number Original line Diff line number Diff line Loading @@ -106,8 +106,26 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; #define AZX_REG_HSW_EM4 0x100c #define AZX_REG_HSW_EM4 0x100c #define AZX_REG_HSW_EM5 0x1010 #define AZX_REG_HSW_EM5 0x1010 /* Skylake/Broxton display HD-A controller Extended Mode registers */ /* Skylake/Broxton vendor-specific registers */ #define AZX_REG_SKL_EM4L 0x1040 #define AZX_REG_VS_EM1 0x1000 #define AZX_REG_VS_INRC 0x1004 #define AZX_REG_VS_OUTRC 0x1008 #define AZX_REG_VS_FIFOTRK 0x100C #define AZX_REG_VS_FIFOTRK2 0x1010 #define AZX_REG_VS_EM2 0x1030 #define AZX_REG_VS_EM3L 0x1038 #define AZX_REG_VS_EM3U 0x103C #define AZX_REG_VS_EM4L 0x1040 #define AZX_REG_VS_EM4U 0x1044 #define AZX_REG_VS_LTRC 0x1048 #define AZX_REG_VS_D0I3C 0x104A #define AZX_REG_VS_PCE 0x104B #define AZX_REG_VS_L2MAGC 0x1050 #define AZX_REG_VS_L2LAHPT 0x1054 #define AZX_REG_VS_SDXDPIB_XBASE 0x1084 #define AZX_REG_VS_SDXDPIB_XINTERVAL 0x20 #define AZX_REG_VS_SDXEFIFOS_XBASE 0x1094 #define AZX_REG_VS_SDXEFIFOS_XINTERVAL 0x20 /* PCI space */ /* PCI space */ #define AZX_PCIREG_TCSEL 0x44 #define AZX_PCIREG_TCSEL 0x44 Loading Loading @@ -243,9 +261,11 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; #define AZX_REG_ML_LOUTPAY 0x20 #define AZX_REG_ML_LOUTPAY 0x20 #define AZX_REG_ML_LINPAY 0x30 #define AZX_REG_ML_LINPAY 0x30 #define AZX_MLCTL_SPA (1<<16) #define ML_LCTL_SCF_MASK 0xF #define AZX_MLCTL_CPA 23 #define AZX_MLCTL_SPA (0x1 << 16) #define AZX_MLCTL_CPA (0x1 << 23) #define AZX_MLCTL_SPA_SHIFT 16 #define AZX_MLCTL_CPA_SHIFT 23 /* registers for DMA Resume Capability Structure */ /* registers for DMA Resume Capability Structure */ #define AZX_DRSM_CAP_ID 0x5 #define AZX_DRSM_CAP_ID 0x5 Loading include/sound/hdaudio.h +18 −10 Original line number Original line Diff line number Diff line Loading @@ -368,24 +368,32 @@ void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus); /* /* * macros for easy use * macros for easy use */ */ #define _snd_hdac_chip_write(type, chip, reg, value) \ #define _snd_hdac_chip_writeb(chip, reg, value) \ ((chip)->io_ops->reg_write ## type(value, (chip)->remap_addr + (reg))) ((chip)->io_ops->reg_writeb(value, (chip)->remap_addr + (reg))) #define _snd_hdac_chip_read(type, chip, reg) \ #define _snd_hdac_chip_readb(chip, reg) \ ((chip)->io_ops->reg_read ## type((chip)->remap_addr + (reg))) ((chip)->io_ops->reg_readb((chip)->remap_addr + (reg))) #define _snd_hdac_chip_writew(chip, reg, value) \ ((chip)->io_ops->reg_writew(value, (chip)->remap_addr + (reg))) #define _snd_hdac_chip_readw(chip, reg) \ ((chip)->io_ops->reg_readw((chip)->remap_addr + (reg))) #define _snd_hdac_chip_writel(chip, reg, value) \ ((chip)->io_ops->reg_writel(value, (chip)->remap_addr + (reg))) #define _snd_hdac_chip_readl(chip, reg) \ ((chip)->io_ops->reg_readl((chip)->remap_addr + (reg))) /* read/write a register, pass without AZX_REG_ prefix */ /* read/write a register, pass without AZX_REG_ prefix */ #define snd_hdac_chip_writel(chip, reg, value) \ #define snd_hdac_chip_writel(chip, reg, value) \ _snd_hdac_chip_write(l, chip, AZX_REG_ ## reg, value) _snd_hdac_chip_writel(chip, AZX_REG_ ## reg, value) #define snd_hdac_chip_writew(chip, reg, value) \ #define snd_hdac_chip_writew(chip, reg, value) \ _snd_hdac_chip_write(w, chip, AZX_REG_ ## reg, value) _snd_hdac_chip_writew(chip, AZX_REG_ ## reg, value) #define snd_hdac_chip_writeb(chip, reg, value) \ #define snd_hdac_chip_writeb(chip, reg, value) \ _snd_hdac_chip_write(b, chip, AZX_REG_ ## reg, value) _snd_hdac_chip_writeb(chip, AZX_REG_ ## reg, value) #define snd_hdac_chip_readl(chip, reg) \ #define snd_hdac_chip_readl(chip, reg) \ _snd_hdac_chip_read(l, chip, AZX_REG_ ## reg) _snd_hdac_chip_readl(chip, AZX_REG_ ## reg) #define snd_hdac_chip_readw(chip, reg) \ #define snd_hdac_chip_readw(chip, reg) \ _snd_hdac_chip_read(w, chip, AZX_REG_ ## reg) _snd_hdac_chip_readw(chip, AZX_REG_ ## reg) #define snd_hdac_chip_readb(chip, reg) \ #define snd_hdac_chip_readb(chip, reg) \ _snd_hdac_chip_read(b, chip, AZX_REG_ ## reg) _snd_hdac_chip_readb(chip, AZX_REG_ ## reg) /* update a register, pass without AZX_REG_ prefix */ /* update a register, pass without AZX_REG_ prefix */ #define snd_hdac_chip_updatel(chip, reg, mask, val) \ #define snd_hdac_chip_updatel(chip, reg, mask, val) \ Loading include/uapi/sound/asound.h +3 −1 Original line number Original line Diff line number Diff line Loading @@ -107,9 +107,11 @@ enum { SNDRV_HWDEP_IFACE_FW_DIGI00X, /* Digidesign Digi 002/003 family */ SNDRV_HWDEP_IFACE_FW_DIGI00X, /* Digidesign Digi 002/003 family */ SNDRV_HWDEP_IFACE_FW_TASCAM, /* TASCAM FireWire series */ SNDRV_HWDEP_IFACE_FW_TASCAM, /* TASCAM FireWire series */ SNDRV_HWDEP_IFACE_LINE6, /* Line6 USB processors */ SNDRV_HWDEP_IFACE_LINE6, /* Line6 USB processors */ SNDRV_HWDEP_IFACE_FW_MOTU, /* MOTU FireWire series */ SNDRV_HWDEP_IFACE_FW_FIREFACE, /* RME Fireface series */ /* Don't forget to change the following: */ /* Don't forget to change the following: */ SNDRV_HWDEP_IFACE_LAST = SNDRV_HWDEP_IFACE_LINE6 SNDRV_HWDEP_IFACE_LAST = SNDRV_HWDEP_IFACE_FW_FIREFACE }; }; struct snd_hwdep_info { struct snd_hwdep_info { Loading include/uapi/sound/firewire.h +9 −1 Original line number Original line Diff line number Diff line Loading @@ -10,6 +10,7 @@ #define SNDRV_FIREWIRE_EVENT_DICE_NOTIFICATION 0xd1ce004e #define SNDRV_FIREWIRE_EVENT_DICE_NOTIFICATION 0xd1ce004e #define SNDRV_FIREWIRE_EVENT_EFW_RESPONSE 0x4e617475 #define SNDRV_FIREWIRE_EVENT_EFW_RESPONSE 0x4e617475 #define SNDRV_FIREWIRE_EVENT_DIGI00X_MESSAGE 0x746e736c #define SNDRV_FIREWIRE_EVENT_DIGI00X_MESSAGE 0x746e736c #define SNDRV_FIREWIRE_EVENT_MOTU_NOTIFICATION 0x64776479 struct snd_firewire_event_common { struct snd_firewire_event_common { unsigned int type; /* SNDRV_FIREWIRE_EVENT_xxx */ unsigned int type; /* SNDRV_FIREWIRE_EVENT_xxx */ Loading Loading @@ -46,12 +47,18 @@ struct snd_firewire_event_digi00x_message { __u32 message; /* Digi00x-specific message */ __u32 message; /* Digi00x-specific message */ }; }; struct snd_firewire_event_motu_notification { unsigned int type; __u32 message; /* MOTU-specific bits. */ }; union snd_firewire_event { union snd_firewire_event { struct snd_firewire_event_common common; struct snd_firewire_event_common common; struct snd_firewire_event_lock_status lock_status; struct snd_firewire_event_lock_status lock_status; struct snd_firewire_event_dice_notification dice_notification; struct snd_firewire_event_dice_notification dice_notification; struct snd_firewire_event_efw_response efw_response; struct snd_firewire_event_efw_response efw_response; struct snd_firewire_event_digi00x_message digi00x_message; struct snd_firewire_event_digi00x_message digi00x_message; struct snd_firewire_event_motu_notification motu_notification; }; }; Loading @@ -65,7 +72,8 @@ union snd_firewire_event { #define SNDRV_FIREWIRE_TYPE_OXFW 4 #define SNDRV_FIREWIRE_TYPE_OXFW 4 #define SNDRV_FIREWIRE_TYPE_DIGI00X 5 #define SNDRV_FIREWIRE_TYPE_DIGI00X 5 #define SNDRV_FIREWIRE_TYPE_TASCAM 6 #define SNDRV_FIREWIRE_TYPE_TASCAM 6 /* RME, MOTU, ... */ #define SNDRV_FIREWIRE_TYPE_MOTU 7 #define SNDRV_FIREWIRE_TYPE_FIREFACE 8 struct snd_firewire_get_info { struct snd_firewire_get_info { unsigned int type; /* SNDRV_FIREWIRE_TYPE_xxx */ unsigned int type; /* SNDRV_FIREWIRE_TYPE_xxx */ Loading Loading
Documentation/sound/hd-audio/notes.rst +2 −0 Original line number Original line Diff line number Diff line Loading @@ -494,6 +494,8 @@ add_hp_mic (bool) hp_mic_detect (bool) hp_mic_detect (bool) enable/disable the hp/mic shared input for a single built-in mic enable/disable the hp/mic shared input for a single built-in mic case; default true case; default true vmaster (bool) enable/disable the virtual Master control; default true mixer_nid (int) mixer_nid (int) specifies the widget NID of the analog-loopback mixer specifies the widget NID of the analog-loopback mixer Loading
include/sound/hda_register.h +25 −5 Original line number Original line Diff line number Diff line Loading @@ -106,8 +106,26 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; #define AZX_REG_HSW_EM4 0x100c #define AZX_REG_HSW_EM4 0x100c #define AZX_REG_HSW_EM5 0x1010 #define AZX_REG_HSW_EM5 0x1010 /* Skylake/Broxton display HD-A controller Extended Mode registers */ /* Skylake/Broxton vendor-specific registers */ #define AZX_REG_SKL_EM4L 0x1040 #define AZX_REG_VS_EM1 0x1000 #define AZX_REG_VS_INRC 0x1004 #define AZX_REG_VS_OUTRC 0x1008 #define AZX_REG_VS_FIFOTRK 0x100C #define AZX_REG_VS_FIFOTRK2 0x1010 #define AZX_REG_VS_EM2 0x1030 #define AZX_REG_VS_EM3L 0x1038 #define AZX_REG_VS_EM3U 0x103C #define AZX_REG_VS_EM4L 0x1040 #define AZX_REG_VS_EM4U 0x1044 #define AZX_REG_VS_LTRC 0x1048 #define AZX_REG_VS_D0I3C 0x104A #define AZX_REG_VS_PCE 0x104B #define AZX_REG_VS_L2MAGC 0x1050 #define AZX_REG_VS_L2LAHPT 0x1054 #define AZX_REG_VS_SDXDPIB_XBASE 0x1084 #define AZX_REG_VS_SDXDPIB_XINTERVAL 0x20 #define AZX_REG_VS_SDXEFIFOS_XBASE 0x1094 #define AZX_REG_VS_SDXEFIFOS_XINTERVAL 0x20 /* PCI space */ /* PCI space */ #define AZX_PCIREG_TCSEL 0x44 #define AZX_PCIREG_TCSEL 0x44 Loading Loading @@ -243,9 +261,11 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; #define AZX_REG_ML_LOUTPAY 0x20 #define AZX_REG_ML_LOUTPAY 0x20 #define AZX_REG_ML_LINPAY 0x30 #define AZX_REG_ML_LINPAY 0x30 #define AZX_MLCTL_SPA (1<<16) #define ML_LCTL_SCF_MASK 0xF #define AZX_MLCTL_CPA 23 #define AZX_MLCTL_SPA (0x1 << 16) #define AZX_MLCTL_CPA (0x1 << 23) #define AZX_MLCTL_SPA_SHIFT 16 #define AZX_MLCTL_CPA_SHIFT 23 /* registers for DMA Resume Capability Structure */ /* registers for DMA Resume Capability Structure */ #define AZX_DRSM_CAP_ID 0x5 #define AZX_DRSM_CAP_ID 0x5 Loading
include/sound/hdaudio.h +18 −10 Original line number Original line Diff line number Diff line Loading @@ -368,24 +368,32 @@ void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus); /* /* * macros for easy use * macros for easy use */ */ #define _snd_hdac_chip_write(type, chip, reg, value) \ #define _snd_hdac_chip_writeb(chip, reg, value) \ ((chip)->io_ops->reg_write ## type(value, (chip)->remap_addr + (reg))) ((chip)->io_ops->reg_writeb(value, (chip)->remap_addr + (reg))) #define _snd_hdac_chip_read(type, chip, reg) \ #define _snd_hdac_chip_readb(chip, reg) \ ((chip)->io_ops->reg_read ## type((chip)->remap_addr + (reg))) ((chip)->io_ops->reg_readb((chip)->remap_addr + (reg))) #define _snd_hdac_chip_writew(chip, reg, value) \ ((chip)->io_ops->reg_writew(value, (chip)->remap_addr + (reg))) #define _snd_hdac_chip_readw(chip, reg) \ ((chip)->io_ops->reg_readw((chip)->remap_addr + (reg))) #define _snd_hdac_chip_writel(chip, reg, value) \ ((chip)->io_ops->reg_writel(value, (chip)->remap_addr + (reg))) #define _snd_hdac_chip_readl(chip, reg) \ ((chip)->io_ops->reg_readl((chip)->remap_addr + (reg))) /* read/write a register, pass without AZX_REG_ prefix */ /* read/write a register, pass without AZX_REG_ prefix */ #define snd_hdac_chip_writel(chip, reg, value) \ #define snd_hdac_chip_writel(chip, reg, value) \ _snd_hdac_chip_write(l, chip, AZX_REG_ ## reg, value) _snd_hdac_chip_writel(chip, AZX_REG_ ## reg, value) #define snd_hdac_chip_writew(chip, reg, value) \ #define snd_hdac_chip_writew(chip, reg, value) \ _snd_hdac_chip_write(w, chip, AZX_REG_ ## reg, value) _snd_hdac_chip_writew(chip, AZX_REG_ ## reg, value) #define snd_hdac_chip_writeb(chip, reg, value) \ #define snd_hdac_chip_writeb(chip, reg, value) \ _snd_hdac_chip_write(b, chip, AZX_REG_ ## reg, value) _snd_hdac_chip_writeb(chip, AZX_REG_ ## reg, value) #define snd_hdac_chip_readl(chip, reg) \ #define snd_hdac_chip_readl(chip, reg) \ _snd_hdac_chip_read(l, chip, AZX_REG_ ## reg) _snd_hdac_chip_readl(chip, AZX_REG_ ## reg) #define snd_hdac_chip_readw(chip, reg) \ #define snd_hdac_chip_readw(chip, reg) \ _snd_hdac_chip_read(w, chip, AZX_REG_ ## reg) _snd_hdac_chip_readw(chip, AZX_REG_ ## reg) #define snd_hdac_chip_readb(chip, reg) \ #define snd_hdac_chip_readb(chip, reg) \ _snd_hdac_chip_read(b, chip, AZX_REG_ ## reg) _snd_hdac_chip_readb(chip, AZX_REG_ ## reg) /* update a register, pass without AZX_REG_ prefix */ /* update a register, pass without AZX_REG_ prefix */ #define snd_hdac_chip_updatel(chip, reg, mask, val) \ #define snd_hdac_chip_updatel(chip, reg, mask, val) \ Loading
include/uapi/sound/asound.h +3 −1 Original line number Original line Diff line number Diff line Loading @@ -107,9 +107,11 @@ enum { SNDRV_HWDEP_IFACE_FW_DIGI00X, /* Digidesign Digi 002/003 family */ SNDRV_HWDEP_IFACE_FW_DIGI00X, /* Digidesign Digi 002/003 family */ SNDRV_HWDEP_IFACE_FW_TASCAM, /* TASCAM FireWire series */ SNDRV_HWDEP_IFACE_FW_TASCAM, /* TASCAM FireWire series */ SNDRV_HWDEP_IFACE_LINE6, /* Line6 USB processors */ SNDRV_HWDEP_IFACE_LINE6, /* Line6 USB processors */ SNDRV_HWDEP_IFACE_FW_MOTU, /* MOTU FireWire series */ SNDRV_HWDEP_IFACE_FW_FIREFACE, /* RME Fireface series */ /* Don't forget to change the following: */ /* Don't forget to change the following: */ SNDRV_HWDEP_IFACE_LAST = SNDRV_HWDEP_IFACE_LINE6 SNDRV_HWDEP_IFACE_LAST = SNDRV_HWDEP_IFACE_FW_FIREFACE }; }; struct snd_hwdep_info { struct snd_hwdep_info { Loading
include/uapi/sound/firewire.h +9 −1 Original line number Original line Diff line number Diff line Loading @@ -10,6 +10,7 @@ #define SNDRV_FIREWIRE_EVENT_DICE_NOTIFICATION 0xd1ce004e #define SNDRV_FIREWIRE_EVENT_DICE_NOTIFICATION 0xd1ce004e #define SNDRV_FIREWIRE_EVENT_EFW_RESPONSE 0x4e617475 #define SNDRV_FIREWIRE_EVENT_EFW_RESPONSE 0x4e617475 #define SNDRV_FIREWIRE_EVENT_DIGI00X_MESSAGE 0x746e736c #define SNDRV_FIREWIRE_EVENT_DIGI00X_MESSAGE 0x746e736c #define SNDRV_FIREWIRE_EVENT_MOTU_NOTIFICATION 0x64776479 struct snd_firewire_event_common { struct snd_firewire_event_common { unsigned int type; /* SNDRV_FIREWIRE_EVENT_xxx */ unsigned int type; /* SNDRV_FIREWIRE_EVENT_xxx */ Loading Loading @@ -46,12 +47,18 @@ struct snd_firewire_event_digi00x_message { __u32 message; /* Digi00x-specific message */ __u32 message; /* Digi00x-specific message */ }; }; struct snd_firewire_event_motu_notification { unsigned int type; __u32 message; /* MOTU-specific bits. */ }; union snd_firewire_event { union snd_firewire_event { struct snd_firewire_event_common common; struct snd_firewire_event_common common; struct snd_firewire_event_lock_status lock_status; struct snd_firewire_event_lock_status lock_status; struct snd_firewire_event_dice_notification dice_notification; struct snd_firewire_event_dice_notification dice_notification; struct snd_firewire_event_efw_response efw_response; struct snd_firewire_event_efw_response efw_response; struct snd_firewire_event_digi00x_message digi00x_message; struct snd_firewire_event_digi00x_message digi00x_message; struct snd_firewire_event_motu_notification motu_notification; }; }; Loading @@ -65,7 +72,8 @@ union snd_firewire_event { #define SNDRV_FIREWIRE_TYPE_OXFW 4 #define SNDRV_FIREWIRE_TYPE_OXFW 4 #define SNDRV_FIREWIRE_TYPE_DIGI00X 5 #define SNDRV_FIREWIRE_TYPE_DIGI00X 5 #define SNDRV_FIREWIRE_TYPE_TASCAM 6 #define SNDRV_FIREWIRE_TYPE_TASCAM 6 /* RME, MOTU, ... */ #define SNDRV_FIREWIRE_TYPE_MOTU 7 #define SNDRV_FIREWIRE_TYPE_FIREFACE 8 struct snd_firewire_get_info { struct snd_firewire_get_info { unsigned int type; /* SNDRV_FIREWIRE_TYPE_xxx */ unsigned int type; /* SNDRV_FIREWIRE_TYPE_xxx */ Loading