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Commit d5c87390 authored by Huang Rui's avatar Huang Rui Committed by Alex Deucher
Browse files

drm/amdgpu: abstract disable identity aperture for gfxhub/mmhub 



Signed-off-by: default avatarHuang Rui <ray.huang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 02c4704b

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

+21 −16
Original line number Diff line number Diff line
@@ -175,6 +175,26 @@ static void gfxhub_v1_0_enable_system_domain(struct amdgpu_device *adev) 
	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL), tmp);

}



static void gfxhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev)

{

	WREG32(SOC15_REG_OFFSET(GC, 0,

				mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32),

	       0XFFFFFFFF);

	WREG32(SOC15_REG_OFFSET(GC, 0,

		mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32), 0x0000000F);



	WREG32(SOC15_REG_OFFSET(GC, 0,

		mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32), 0);

	WREG32(SOC15_REG_OFFSET(GC, 0,

		mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32), 0);



	WREG32(SOC15_REG_OFFSET(GC, 0,

		mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32), 0);

	WREG32(SOC15_REG_OFFSET(GC, 0,

		mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32), 0);



}



int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)

{

	u32 tmp;
@@ -199,22 +219,7 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev) 
	gfxhub_v1_0_init_cache_regs(adev);



	gfxhub_v1_0_enable_system_domain(adev);



	/* Disable identity aperture.*/

	WREG32(SOC15_REG_OFFSET(GC, 0,

		mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32), 0XFFFFFFFF);

	WREG32(SOC15_REG_OFFSET(GC, 0,

		mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32), 0x0000000F);



	WREG32(SOC15_REG_OFFSET(GC, 0,

		mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32), 0);

	WREG32(SOC15_REG_OFFSET(GC, 0,

		mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32), 0);



	WREG32(SOC15_REG_OFFSET(GC, 0,

		mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32), 0);

	WREG32(SOC15_REG_OFFSET(GC, 0,

		mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32), 0);

	gfxhub_v1_0_disable_identity_aperture(adev);



	for (i = 0; i <= 14; i++) {

		tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL) + i);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

+20 −16
Original line number Diff line number Diff line
@@ -186,6 +186,25 @@ static void mmhub_v1_0_enable_system_domain(struct amdgpu_device *adev) 
	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL), tmp);

}



static void mmhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev)

{

	WREG32(SOC15_REG_OFFSET(MMHUB, 0,

				mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32),

	       0XFFFFFFFF);

	WREG32(SOC15_REG_OFFSET(MMHUB, 0,

		mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32), 0x0000000F);



	WREG32(SOC15_REG_OFFSET(MMHUB, 0,

		mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32), 0);

	WREG32(SOC15_REG_OFFSET(MMHUB, 0,

		mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32), 0);



	WREG32(SOC15_REG_OFFSET(MMHUB, 0,

		mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32), 0);

	WREG32(SOC15_REG_OFFSET(MMHUB, 0,

		mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32), 0);

}



int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)

{

	u32 tmp;
@@ -210,22 +229,7 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev) 
	mmhub_v1_0_init_cache_regs(adev);



	mmhub_v1_0_enable_system_domain(adev);



	/* Disable identity aperture.*/

	WREG32(SOC15_REG_OFFSET(MMHUB, 0,

		mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32), 0XFFFFFFFF);

	WREG32(SOC15_REG_OFFSET(MMHUB, 0,

		mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32), 0x0000000F);



	WREG32(SOC15_REG_OFFSET(MMHUB, 0,

		mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32), 0);

	WREG32(SOC15_REG_OFFSET(MMHUB, 0,

		mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32), 0);



	WREG32(SOC15_REG_OFFSET(MMHUB, 0,

		mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32), 0);

	WREG32(SOC15_REG_OFFSET(MMHUB, 0,

		mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32), 0);

	mmhub_v1_0_disable_identity_aperture(adev);



	for (i = 0; i <= 14; i++) {

		tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL)