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Commit 02c4704b authored by Huang Rui's avatar Huang Rui Committed by Alex Deucher
Browse files

drm/amdgpu: abstract system domain enablement for gfxhub/mmhub 



Signed-off-by: default avatarHuang Rui <ray.huang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 41f6f311

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

+16 −6
Original line number Diff line number Diff line
@@ -165,14 +165,27 @@ static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev) 
	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL4), tmp);

}



static void gfxhub_v1_0_enable_system_domain(struct amdgpu_device *adev)

{

	uint32_t tmp;



	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL));

	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);

	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL), tmp);

}



int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)

{

	u32 tmp;

	u32 i;



	if (amdgpu_sriov_vf(adev)) {

		/* MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are VF copy registers so

		vbios post doesn't program them, for SRIOV driver need to program them */

		/*

		 * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are

		 * VF copy registers so vbios post doesn't program them, for

		 * SRIOV driver need to program them

		 */

		WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_BASE),

				adev->mc.vram_start >> 24);

		WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_TOP),
@@ -185,10 +198,7 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev) 
	gfxhub_v1_0_init_tlb_regs(adev);

	gfxhub_v1_0_init_cache_regs(adev);



	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL));

	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);

	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL), tmp);

	gfxhub_v1_0_enable_system_domain(adev);



	/* Disable identity aperture.*/

	WREG32(SOC15_REG_OFFSET(GC, 0,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

+16 −11
Original line number Diff line number Diff line
@@ -176,15 +176,27 @@ static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev) 
	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL4), tmp);

}



static void mmhub_v1_0_enable_system_domain(struct amdgpu_device *adev)

{

	uint32_t tmp;



	tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL));

	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);

	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL), tmp);

}



int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)

{

	u32 tmp;

	uint64_t addr;

	u32 i;



	if (amdgpu_sriov_vf(adev)) {

		/* MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are VF copy registers so

		vbios post doesn't program them, for SRIOV driver need to program them */

		/*

		 * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are

		 * VF copy registers so vbios post doesn't program them, for

		 * SRIOV driver need to program them

		 */

		WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE),

			adev->mc.vram_start >> 24);

		WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP),
@@ -197,14 +209,7 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev) 
	mmhub_v1_0_init_tlb_regs(adev);

	mmhub_v1_0_init_cache_regs(adev);



	addr = SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL);

	tmp = RREG32(addr);



	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);

	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL), tmp);



	tmp = RREG32(addr);

	mmhub_v1_0_enable_system_domain(adev);



	/* Disable identity aperture.*/

	WREG32(SOC15_REG_OFFSET(MMHUB, 0,