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Commit 41f6f311 authored by Huang Rui's avatar Huang Rui Committed by Alex Deucher
Browse files

drm/amdgpu: abstract cache initialization for gfxhub/mmhub 



Signed-off-by: default avatarHuang Rui <ray.huang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 34269839

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

+31 −41
Original line number Diff line number Diff line
@@ -135,45 +135,20 @@ static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device *adev) 
	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp);

}



int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)

static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev)

{

	u32 tmp;

	u32 i;



	if (amdgpu_sriov_vf(adev)) {

		/* MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are VF copy registers so

		vbios post doesn't program them, for SRIOV driver need to program them */

		WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_BASE),

				adev->mc.vram_start >> 24);

		WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_TOP),

				adev->mc.vram_end >> 24);

	}



	/* GART Enable. */

	gfxhub_v1_0_init_gart_aperture_regs(adev);

	gfxhub_v1_0_init_system_aperture_regs(adev);

	gfxhub_v1_0_init_tlb_regs(adev);

	uint32_t tmp;



	/* Setup L2 cache */

	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL));

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);

	tmp = REG_SET_FIELD(tmp,

				VM_L2_CNTL,

				ENABLE_L2_FRAGMENT_PROCESSING,

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);

	/* XXX for emulation, Refer to closed source code.*/

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,

			    0);

	tmp = REG_SET_FIELD(tmp,

				VM_L2_CNTL,

				L2_PDE0_CACHE_TAG_GENERATION_MODE,

				0);/* XXX for emulation, Refer to closed source code.*/

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);

	tmp = REG_SET_FIELD(tmp,

				VM_L2_CNTL,

				CONTEXT1_IDENTITY_ACCESS_MODE,

				1);

	tmp = REG_SET_FIELD(tmp,

				VM_L2_CNTL,

				IDENTITY_MODE_FRAGMENT_SIZE,

				0);

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);

	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL), tmp);



	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL2));
@@ -184,16 +159,31 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev) 
	tmp = mmVM_L2_CNTL3_DEFAULT;

	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL3), tmp);



	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL4));

	tmp = REG_SET_FIELD(tmp,

			    VM_L2_CNTL4,

			    VMC_TAP_PDE_REQUEST_PHYSICAL,

			    0);

	tmp = REG_SET_FIELD(tmp,

			    VM_L2_CNTL4,

			    VMC_TAP_PTE_REQUEST_PHYSICAL,

			    0);

	tmp = mmVM_L2_CNTL4_DEFAULT;

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);

	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL4), tmp);

}



int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)

{

	u32 tmp;

	u32 i;



	if (amdgpu_sriov_vf(adev)) {

		/* MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are VF copy registers so

		vbios post doesn't program them, for SRIOV driver need to program them */

		WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_BASE),

				adev->mc.vram_start >> 24);

		WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_TOP),

				adev->mc.vram_end >> 24);

	}



	/* GART Enable. */

	gfxhub_v1_0_init_gart_aperture_regs(adev);

	gfxhub_v1_0_init_system_aperture_regs(adev);

	gfxhub_v1_0_init_tlb_regs(adev);

	gfxhub_v1_0_init_cache_regs(adev);



	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL));

	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

+31 −57
Original line number Diff line number Diff line
@@ -146,6 +146,36 @@ static void mmhub_v1_0_init_tlb_regs(struct amdgpu_device *adev) 
	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp);

}



static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev)

{

	uint32_t tmp;



	/* Setup L2 cache */

	tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL));

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);

	/* XXX for emulation, Refer to closed source code.*/

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,

			    0);

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);

	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL), tmp);



	tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL2));

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL2), tmp);



	tmp = mmVM_L2_CNTL3_DEFAULT;

	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL3), tmp);



	tmp = mmVM_L2_CNTL4_DEFAULT;

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);

	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL4), tmp);

}



int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)

{

	u32 tmp;
@@ -165,63 +195,7 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev) 
	mmhub_v1_0_init_gart_aperture_regs(adev);

	mmhub_v1_0_init_system_aperture_regs(adev);

	mmhub_v1_0_init_tlb_regs(adev);



	/* Setup TLB control */

	tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL));



	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);

	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

			    ENABLE_ADVANCED_DRIVER_MODEL, 1);

	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

			    SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);

	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);

	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

			    MTYPE, MTYPE_UC);/* XXX for emulation. */

	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);



	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp);



	/* Setup L2 cache */

	tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL));

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);

	tmp = REG_SET_FIELD(tmp,

				VM_L2_CNTL,

				ENABLE_L2_FRAGMENT_PROCESSING,

				0);

	tmp = REG_SET_FIELD(tmp,

				VM_L2_CNTL,

				L2_PDE0_CACHE_TAG_GENERATION_MODE,

				0);/* XXX for emulation, Refer to closed source code.*/

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);

	tmp = REG_SET_FIELD(tmp,

				VM_L2_CNTL,

				CONTEXT1_IDENTITY_ACCESS_MODE,

				1);

	tmp = REG_SET_FIELD(tmp,

				VM_L2_CNTL,

				IDENTITY_MODE_FRAGMENT_SIZE,

				0);

	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL), tmp);



	tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL2));

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL2), tmp);



	tmp = mmVM_L2_CNTL3_DEFAULT;

	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL3), tmp);



	tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL4));

	tmp = REG_SET_FIELD(tmp,

			    VM_L2_CNTL4,

			    VMC_TAP_PDE_REQUEST_PHYSICAL,

			    0);

	tmp = REG_SET_FIELD(tmp,

			    VM_L2_CNTL4,

			    VMC_TAP_PTE_REQUEST_PHYSICAL,

			    0);

	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL4), tmp);

	mmhub_v1_0_init_cache_regs(adev);



	addr = SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL);

	tmp = RREG32(addr);