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Commit c2053895 authored by Sanchayan Maity's avatar Sanchayan Maity Committed by Shawn Guo
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ARM: imx: clk-vf610: Add clock for SNVS



Add support for clock gating of the SNVS peripheral.

Signed-off-by: default avatarSanchayan Maity <maitysanchayan@gmail.com>
Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
parent 6f540db7
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+2 −0
Original line number Diff line number Diff line
@@ -382,6 +382,8 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
	clk[VF610_CLK_DMAMUX2] = imx_clk_gate2("dmamux2", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(1));
	clk[VF610_CLK_DMAMUX3] = imx_clk_gate2("dmamux3", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(2));

	clk[VF610_CLK_SNVS] = imx_clk_gate2("snvs-rtc", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(7));

	imx_check_clocks(clk, ARRAY_SIZE(clk));

	clk_set_parent(clk[VF610_CLK_QSPI0_SEL], clk[VF610_CLK_PLL1_PFD4]);
+2 −1
Original line number Diff line number Diff line
@@ -192,6 +192,7 @@
#define VF610_PLL5_BYPASS		179
#define VF610_PLL6_BYPASS		180
#define VF610_PLL7_BYPASS		181
#define VF610_CLK_END			182
#define VF610_CLK_SNVS			182
#define VF610_CLK_END			183

#endif /* __DT_BINDINGS_CLOCK_VF610_H */