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Commit bf877293 authored by Jordan Crouse's avatar Jordan Crouse
Browse files

clk: qcom: Fix compile warnings



Fix a handful of these warnings in the PLL definition files:

  format '%x' expects argument of type 'unsigned int', but argument 4 has
	type 'u64 {aka long long unsigned int}' [-Werror=format=]
  pr_debug("vco_cfg0 = 0x%x   vco_cfg4 = 0x%x\n", vco_cfg0, vco_cfg4);

Fixes: 9c8b902a ("clk:qcom: Snapshot of  mdss pll driver")
Fixes: 0fd7ae3f ("clk:qcom: add mdss dsi and dp pll driver support")
Change-Id: Ic0dedbadb611091112bb96fd3817e266b97b2950
Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
parent c4c224ee
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+1 −1
Original line number Diff line number Diff line
@@ -694,7 +694,7 @@ unsigned long dp_vco_recalc_rate_7nm(struct clk_hw *hw,
			vco_rate = DP_VCO_HSCLK_RATE_8100MHZDIV1000;
	}

	pr_debug("hsclk: sel=0x%x, div=0x%x; lclk: sel=%lu, div=%lu, rate=%lu\n",
	pr_debug("hsclk: sel=0x%x, div=0x%x; lclk: sel=%u, div=%u, rate=%lu\n",
		hsclk_sel, hsclk_div, link_clk_divsel, link_clk_div, vco_rate);

	mdss_pll_resource_enable(dp_res, false);
+4 −4
Original line number Diff line number Diff line
@@ -276,8 +276,8 @@ static void hdmi_phy_pll_calculator_28lpm(unsigned long vco_rate,
	do_div(sdm_cfg2, int_ref_clk_freq);

	pr_debug("lf_cfg0 = 0x%x    lf_cfg1 = 0x%x\n", lf_cfg0, lf_cfg1);
	pr_debug("vco_cfg0 = 0x%x   vco_cfg4 = 0x%x\n", vco_cfg0, vco_cfg4);
	pr_debug("sdm_cfg0 = 0x%x   sdm_cfg1 = 0x%x   sdm_cfg2 = 0x%x\n",
	pr_debug("vco_cfg0 = 0x%llx   vco_cfg4 = 0x%llx\n", vco_cfg0, vco_cfg4);
	pr_debug("sdm_cfg0 = 0x%llx   sdm_cfg1 = 0x%llx   sdm_cfg2 = 0x%llx\n",
				sdm_cfg0, sdm_cfg1, sdm_cfg2);

	refclk_cfg = MDSS_PLL_REG_R(pll_base, HDMI_PHY_PLL_REFCLK_CFG);
@@ -500,7 +500,7 @@ unsigned long hdmi_vco_recalc_rate_28lpm(struct clk_hw *hw,

	if (hdmi_pll_res->vco_current_rate) {
		vco_rate = (unsigned long)hdmi_pll_res->vco_current_rate;
		pr_debug("vco_rate=%ld\n", vco_rate);
		pr_debug("vco_rate=%lld\n", vco_rate);
		return vco_rate;
	}

@@ -521,7 +521,7 @@ unsigned long hdmi_vco_recalc_rate_28lpm(struct clk_hw *hw,
		mdss_pll_resource_enable(hdmi_pll_res, false);
	}

	pr_debug("vco_rate = %ld\n", vco_rate);
	pr_debug("vco_rate = %lld\n", vco_rate);

	return (unsigned long)vco_rate;
}