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Commit 9c8b902a authored by Satya Rama Aditya Pinapala's avatar Satya Rama Aditya Pinapala
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clk:qcom: Snapshot of mdss pll driver 



This snapshot includes mdss pll driver changes for
different nm chipsets. Change also includes updated copyright
year in all files. This snapshot was taken from msm-4.14
as of commit 1df57774a520 ("Merge "ARM: dts: msm: Remove
dma-coherent for IPA for sdxprairie"").

Change-Id: I49c66cd4fa474c464c4c2d55cd8712d214bb791b
Signed-off-by: default avatarSatya Rama Aditya Pinapala <psraditya30@codeaurora.org>
parent e222d4df

drivers/clk/qcom/mdss/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -8,7 +8,7 @@ obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-dsi-pll-28lpm.o 
obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-dsi-pll-28nm-util.o

obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-dsi-pll-14nm.o

obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-dsi-pll-14nm-util.o



obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-hdmi-pll-28lpm.o

obj-$(CONFIG_QCOM_MDSS_DP_PLL) += mdss-dp-pll-7nm.o \

	mdss-dp-pll-7nm-util.o \

	mdss-dp-pll-10nm.o \

drivers/clk/qcom/mdss/mdss-dp-pll-14nm.c

+21 −68
Original line number Diff line number Diff line
@@ -93,7 +93,7 @@ static struct dp_pll_vco_clk dp_vco_clk = { 
};



static struct clk_fixed_factor dp_phy_pll_link_clk = {

	.div = 5,

	.div = 10,

	.mult = 1,



	.hw.init = &(struct clk_init_data){
@@ -284,6 +284,7 @@ static int dp_vco_pll_init_db_14nm(struct dp_pll_db *pdb, 
		pdb->lock_cmp2_mode0 = 0x21;

		pdb->lock_cmp3_mode0 = 0x00;

		pdb->phy_vco_div = 0x1;

		pdb->lane_mode_1 = 0xc6;

		break;

	case DP_VCO_HSCLK_RATE_2700MHZDIV1000:

		pdb->hsclk_sel = 0x24;
@@ -295,6 +296,7 @@ static int dp_vco_pll_init_db_14nm(struct dp_pll_db *pdb, 
		pdb->lock_cmp2_mode0 = 0x38;

		pdb->lock_cmp3_mode0 = 0x00;

		pdb->phy_vco_div = 0x1;

		pdb->lane_mode_1 = 0xc4;

		break;

	case DP_VCO_HSCLK_RATE_5400MHZDIV1000:

		pdb->hsclk_sel = 0x20;
@@ -306,6 +308,7 @@ static int dp_vco_pll_init_db_14nm(struct dp_pll_db *pdb, 
		pdb->lock_cmp2_mode0 = 0x70;

		pdb->lock_cmp3_mode0 = 0x00;

		pdb->phy_vco_div = 0x2;

		pdb->lane_mode_1 = 0xc4;

		break;

	default:

		return -EINVAL;
@@ -326,17 +329,7 @@ int dp_config_vco_rate_14nm(struct dp_pll_vco_clk *vco, 
		return res;

	}



	if (pdb->lane_cnt != 4) {

		if (pdb->orientation == ORIENTATION_CC2)

			MDSS_PLL_REG_W(dp_res->phy_base,

				DP_PHY_PD_CTL, 0x2d);

		else

			MDSS_PLL_REG_W(dp_res->phy_base,

				DP_PHY_PD_CTL, 0x35);

	} else {

		MDSS_PLL_REG_W(dp_res->phy_base,

			DP_PHY_PD_CTL, 0x3d);

	}

	MDSS_PLL_REG_W(dp_res->phy_base, DP_PHY_PD_CTL, 0x3d);



	/* Make sure the PHY register writes are done */

	wmb();
@@ -411,9 +404,9 @@ int dp_config_vco_rate_14nm(struct dp_pll_vco_clk *vco, 
	wmb(); /* make sure write happens */



	if (pdb->orientation == ORIENTATION_CC2)

		MDSS_PLL_REG_W(dp_res->phy_base, DP_PHY_MODE, 0xc8);

		MDSS_PLL_REG_W(dp_res->phy_base, DP_PHY_MODE, 0xc9);

	else

		MDSS_PLL_REG_W(dp_res->phy_base, DP_PHY_MODE, 0xd8);

		MDSS_PLL_REG_W(dp_res->phy_base, DP_PHY_MODE, 0xd9);

	wmb(); /* make sure write happens */



	/* TX Lane configuration */
@@ -538,10 +531,8 @@ static bool dp_14nm_phy_rdy_status(struct mdss_pll_resources *dp_res) 
static int dp_pll_enable_14nm(struct clk_hw *hw)

{

	int rc = 0;

	u32 bias_en, drvr_en;

	struct dp_pll_vco_clk *vco = to_dp_vco_hw(hw);

	struct mdss_pll_resources *dp_res = vco->priv;

	struct dp_pll_db *pdb = (struct dp_pll_db *)dp_res->priv;



	MDSS_PLL_REG_W(dp_res->phy_base, DP_PHY_CFG, 0x01);

	MDSS_PLL_REG_W(dp_res->phy_base, DP_PHY_CFG, 0x05);
@@ -572,36 +563,14 @@ static int dp_pll_enable_14nm(struct clk_hw *hw) 


	pr_debug("PLL is locked\n");



	if (pdb->lane_cnt == 1) {

		bias_en = 0x3e;

		drvr_en = 0x13;

	} else {

		bias_en = 0x3f;

		drvr_en = 0x10;

	}



	if (pdb->lane_cnt != 4) {

		if (pdb->orientation == ORIENTATION_CC1) {

			MDSS_PLL_REG_W(dp_res->phy_base,

			QSERDES_TX1_OFFSET + TXn_TRANSCEIVER_BIAS_EN, bias_en);

			MDSS_PLL_REG_W(dp_res->phy_base,

			QSERDES_TX1_OFFSET + TXn_HIGHZ_DRVR_EN, drvr_en);

		} else {

			MDSS_PLL_REG_W(dp_res->phy_base,

			QSERDES_TX0_OFFSET + TXn_TRANSCEIVER_BIAS_EN, bias_en);

	MDSS_PLL_REG_W(dp_res->phy_base,

			QSERDES_TX0_OFFSET + TXn_HIGHZ_DRVR_EN, drvr_en);

		}

	} else {

		QSERDES_TX0_OFFSET + TXn_TRANSCEIVER_BIAS_EN, 0x3f);

	MDSS_PLL_REG_W(dp_res->phy_base,

			QSERDES_TX0_OFFSET + TXn_TRANSCEIVER_BIAS_EN, bias_en);

		QSERDES_TX0_OFFSET + TXn_HIGHZ_DRVR_EN, 0x10);

	MDSS_PLL_REG_W(dp_res->phy_base,

			QSERDES_TX0_OFFSET + TXn_HIGHZ_DRVR_EN, drvr_en);

		QSERDES_TX1_OFFSET + TXn_TRANSCEIVER_BIAS_EN, 0x3f);

	MDSS_PLL_REG_W(dp_res->phy_base,

			QSERDES_TX1_OFFSET + TXn_TRANSCEIVER_BIAS_EN, bias_en);

		MDSS_PLL_REG_W(dp_res->phy_base,

			QSERDES_TX1_OFFSET + TXn_HIGHZ_DRVR_EN, drvr_en);

	}

		QSERDES_TX1_OFFSET + TXn_HIGHZ_DRVR_EN, 0x10);



	MDSS_PLL_REG_W(dp_res->phy_base,

		QSERDES_TX0_OFFSET + TXn_TX_POL_INV, 0x0a);
@@ -730,7 +699,7 @@ unsigned long dp_vco_recalc_rate_14nm(struct clk_hw *hw, 
{

	struct dp_pll_vco_clk *vco = to_dp_vco_hw(hw);

	int rc;

	u32 div, hsclk_div, link2xclk_div = 0;

	u32 div, hsclk_div;

	u64 vco_rate;

	struct mdss_pll_resources *dp_res = vco->priv;
@@ -757,28 +726,12 @@ unsigned long dp_vco_recalc_rate_14nm(struct clk_hw *hw, 
		hsclk_div = 5;

	}



	div = MDSS_PLL_REG_R(dp_res->phy_base, DP_PHY_MODE);



	if (div & 0xd8)

		pr_err("DP PAR Rate not correct\n");



	if ((div & 0x3) == 1)

		link2xclk_div = 10;

	else if ((div & 0x3) == 0)

		link2xclk_div = 5;

	else

		pr_err("unsupported div. Phy_mode: %d\n", div);



	if (link2xclk_div == 10) {

		vco_rate = DP_VCO_HSCLK_RATE_2700MHZDIV1000;

	} else {

	if (hsclk_div == 5)

		vco_rate = DP_VCO_HSCLK_RATE_1620MHZDIV1000;

	else if (hsclk_div == 3)

		vco_rate = DP_VCO_HSCLK_RATE_2700MHZDIV1000;

	else

		vco_rate = DP_VCO_HSCLK_RATE_5400MHZDIV1000;

	}



	pr_debug("returning vco rate = %lu\n", (unsigned long)vco_rate);

drivers/clk/qcom/mdss/mdss-dp-pll-14nm.h

+4 −1
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.

 * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.

 */



#ifndef __MDSS_DP_PLL_14NM_H
@@ -168,6 +168,9 @@ struct dp_pll_db { 


	/* PHY vco divider */

	u32 phy_vco_div;



	/* TX settings */

	u32 lane_mode_1;

};



int dp_vco_set_rate_14nm(struct clk_hw *hw, unsigned long rate,

drivers/clk/qcom/mdss/mdss-dsi-pll-7nm.c

+34 −4
Original line number Diff line number Diff line
@@ -242,6 +242,18 @@ struct dsi_pll_7nm { 
	struct dsi_pll_regs reg_setup;

};



static inline bool dsi_pll_7nm_is_hw_revision_v1(

		struct mdss_pll_resources *rsc)

{

	return (rsc->pll_interface_type == MDSS_DSI_PLL_7NM) ? true : false;

}



static inline bool dsi_pll_7nm_is_hw_revision_v2(

		struct mdss_pll_resources *rsc)

{

	return (rsc->pll_interface_type == MDSS_DSI_PLL_7NM_V2) ? true : false;

}



static inline int pll_reg_read(void *context, unsigned int reg,

					unsigned int *val)

{
@@ -509,7 +521,11 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll, 


	dec = div_u64(dec_multiple, multiplier);



	regs->pll_clock_inverters = 0;

	if (dsi_pll_7nm_is_hw_revision_v1(rsc))

		regs->pll_clock_inverters = 0x0;

	else

		regs->pll_clock_inverters = 0x28;



	regs->pll_lockdet_rate = config->lock_timer;

	regs->decimal_div_start = dec;

	regs->frac_div_start_low = (frac & 0xff);
@@ -595,7 +611,12 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll, 


	MDSS_PLL_REG_W(pll_base, PLL_ANALOG_CONTROLS_FIVE_1, 0x01);

	MDSS_PLL_REG_W(pll_base, PLL_VCO_CONFIG_1, 0x00);



	if (dsi_pll_7nm_is_hw_revision_v1(rsc))

		MDSS_PLL_REG_W(pll_base, PLL_GEAR_BAND_SELECT_CONTROLS, 0x21);

	else

		MDSS_PLL_REG_W(pll_base, PLL_GEAR_BAND_SELECT_CONTROLS, 0x22);



	MDSS_PLL_REG_W(pll_base, PLL_ANALOG_CONTROLS_FIVE, 0x01);

	MDSS_PLL_REG_W(pll_base, PLL_ANALOG_CONTROLS_TWO, 0x03);

	MDSS_PLL_REG_W(pll_base, PLL_ANALOG_CONTROLS_THREE, 0x00);
@@ -616,7 +637,11 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll, 
	MDSS_PLL_REG_W(pll_base, PLL_PFILT, 0x29);

	MDSS_PLL_REG_W(pll_base, PLL_PFILT, 0x2f);

	MDSS_PLL_REG_W(pll_base, PLL_IFILT, 0x2a);

	MDSS_PLL_REG_W(pll_base, PLL_IFILT, 0x3f);



	if (dsi_pll_7nm_is_hw_revision_v1(rsc))

		MDSS_PLL_REG_W(pll_base, PLL_IFILT, 0x30);

	else

		MDSS_PLL_REG_W(pll_base, PLL_IFILT, 0x22);

}



static void dsi_pll_init_val(struct mdss_pll_resources *rsc)
@@ -707,7 +732,12 @@ static void dsi_pll_init_val(struct mdss_pll_resources *rsc) 
	MDSS_PLL_REG_W(pll_base, PLL_PLL_LOCK_MIN_DELAY, 0x00000019);

	MDSS_PLL_REG_W(pll_base, PLL_CLOCK_INVERTERS, 0x00000000);

	MDSS_PLL_REG_W(pll_base, PLL_SPARE_AND_JPC_OVERRIDES, 0x00000000);



	if (dsi_pll_7nm_is_hw_revision_v1(rsc))

		MDSS_PLL_REG_W(pll_base, PLL_BIAS_CONTROL_1, 0x00000066);

	else

		MDSS_PLL_REG_W(pll_base, PLL_BIAS_CONTROL_1, 0x00000040);



	MDSS_PLL_REG_W(pll_base, PLL_BIAS_CONTROL_2, 0x00000020);

	MDSS_PLL_REG_W(pll_base, PLL_ALOG_OBSV_BUS_CTRL_1, 0x00000000);

	MDSS_PLL_REG_W(pll_base, PLL_COMMON_STATUS_ONE, 0x00000000);

drivers/clk/qcom/mdss/mdss-hdmi-pll-28lpm.c

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+790 −0

File added.

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